cpu_init.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Josef Baumgartner <josef.baumgartner@telex.de>
  5. *
  6. * MCF5282 additionals
  7. * (C) Copyright 2005
  8. * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  9. * (c) Copyright 2010
  10. * Arcturus Networks Inc. <www.arcturusnetworks.com>
  11. *
  12. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  13. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  14. * Hayden Fraser (Hayden.Fraser@freescale.com)
  15. *
  16. * MCF5275 additions
  17. * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  18. */
  19. #include <common.h>
  20. #include <cpu_func.h>
  21. #include <watchdog.h>
  22. #include <asm/immap.h>
  23. #include <asm/io.h>
  24. #if defined(CONFIG_CMD_NET)
  25. #include <config.h>
  26. #include <net.h>
  27. #include <asm/fec.h>
  28. #endif
  29. #ifndef CONFIG_M5272
  30. /* Only 5272 Flexbus chipselect is different from the rest */
  31. void init_fbcs(void)
  32. {
  33. fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  34. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  35. && defined(CONFIG_SYS_CS0_CTRL))
  36. out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  37. out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  38. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  39. #else
  40. #warning "Chip Select 0 are not initialized/used"
  41. #endif
  42. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  43. && defined(CONFIG_SYS_CS1_CTRL))
  44. out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  45. out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  46. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  47. #endif
  48. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  49. && defined(CONFIG_SYS_CS2_CTRL))
  50. out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  51. out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  52. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  53. #endif
  54. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  55. && defined(CONFIG_SYS_CS3_CTRL))
  56. out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  57. out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  58. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  59. #endif
  60. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  61. && defined(CONFIG_SYS_CS4_CTRL))
  62. out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  63. out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  64. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  65. #endif
  66. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  67. && defined(CONFIG_SYS_CS5_CTRL))
  68. out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  69. out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  70. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  71. #endif
  72. #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
  73. && defined(CONFIG_SYS_CS6_CTRL))
  74. out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
  75. out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
  76. out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
  77. #endif
  78. #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
  79. && defined(CONFIG_SYS_CS7_CTRL))
  80. out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
  81. out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
  82. out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
  83. #endif
  84. }
  85. #endif
  86. #if defined(CONFIG_M5208)
  87. void cpu_init_f(void)
  88. {
  89. scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  90. #ifndef CONFIG_WATCHDOG
  91. wdog_t *wdg = (wdog_t *) MMAP_WDOG;
  92. /* Disable the watchdog if we aren't using it */
  93. out_be16(&wdg->cr, 0);
  94. #endif
  95. out_be32(&scm1->mpr, 0x77777777);
  96. out_be32(&scm1->pacra, 0);
  97. out_be32(&scm1->pacrb, 0);
  98. out_be32(&scm1->pacrc, 0);
  99. out_be32(&scm1->pacrd, 0);
  100. out_be32(&scm1->pacre, 0);
  101. out_be32(&scm1->pacrf, 0);
  102. /* FlexBus Chipselect */
  103. init_fbcs();
  104. icache_enable();
  105. }
  106. /* initialize higher level parts of CPU like timers */
  107. int cpu_init_r(void)
  108. {
  109. return (0);
  110. }
  111. void uart_port_conf(int port)
  112. {
  113. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  114. /* Setup Ports: */
  115. switch (port) {
  116. case 0:
  117. clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
  118. setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
  119. break;
  120. case 1:
  121. clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
  122. setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
  123. break;
  124. case 2:
  125. #ifdef CONFIG_SYS_UART2_PRI_GPIO
  126. clrbits_8(&gpio->par_timer,
  127. ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
  128. setbits_8(&gpio->par_timer,
  129. GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
  130. #endif
  131. #ifdef CONFIG_SYS_UART2_ALT1_GPIO
  132. clrbits_8(&gpio->par_feci2c,
  133. ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
  134. setbits_8(&gpio->par_feci2c,
  135. GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
  136. #endif
  137. #ifdef CONFIG_SYS_UART2_ALT1_GPIO
  138. clrbits_8(&gpio->par_feci2c,
  139. ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
  140. setbits_8(&gpio->par_feci2c,
  141. GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
  142. #endif
  143. break;
  144. }
  145. }
  146. #if defined(CONFIG_CMD_NET)
  147. int fecpin_setclear(struct eth_device *dev, int setclear)
  148. {
  149. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  150. if (setclear) {
  151. setbits_8(&gpio->par_fec,
  152. GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
  153. setbits_8(&gpio->par_feci2c,
  154. GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
  155. } else {
  156. clrbits_8(&gpio->par_fec,
  157. ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
  158. clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
  159. }
  160. return 0;
  161. }
  162. #endif /* CONFIG_CMD_NET */
  163. #endif /* CONFIG_M5208 */
  164. #if defined(CONFIG_M5253)
  165. /*
  166. * Breath some life into the CPU...
  167. *
  168. * Set up the memory map,
  169. * initialize a bunch of registers,
  170. * initialize the UPM's
  171. */
  172. void cpu_init_f(void)
  173. {
  174. mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
  175. mbar_writeByte(MCFSIM_SYPCR, 0x00);
  176. mbar_writeByte(MCFSIM_SWIVR, 0x0f);
  177. mbar_writeByte(MCFSIM_SWSR, 0x00);
  178. mbar_writeByte(MCFSIM_SWDICR, 0x00);
  179. mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
  180. mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
  181. mbar_writeByte(MCFSIM_I2CICR, 0x00);
  182. mbar_writeByte(MCFSIM_UART1ICR, 0x00);
  183. mbar_writeByte(MCFSIM_UART2ICR, 0x00);
  184. mbar_writeByte(MCFSIM_ICR6, 0x00);
  185. mbar_writeByte(MCFSIM_ICR7, 0x00);
  186. mbar_writeByte(MCFSIM_ICR8, 0x00);
  187. mbar_writeByte(MCFSIM_ICR9, 0x00);
  188. mbar_writeByte(MCFSIM_QSPIICR, 0x00);
  189. mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
  190. mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
  191. mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
  192. /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
  193. /* FlexBus Chipselect */
  194. init_fbcs();
  195. #ifdef CONFIG_SYS_I2C_FSL
  196. CONFIG_SYS_I2C_PINMUX_REG =
  197. CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
  198. CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
  199. #ifdef CONFIG_SYS_I2C2_OFFSET
  200. CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
  201. CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
  202. #endif
  203. #endif
  204. /* enable instruction cache now */
  205. icache_enable();
  206. }
  207. /*initialize higher level parts of CPU like timers */
  208. int cpu_init_r(void)
  209. {
  210. return (0);
  211. }
  212. void uart_port_conf(int port)
  213. {
  214. u32 *par = (u32 *) MMAP_PAR;
  215. /* Setup Ports: */
  216. switch (port) {
  217. case 1:
  218. clrbits_be32(par, 0x00180000);
  219. setbits_be32(par, 0x00180000);
  220. break;
  221. case 2:
  222. clrbits_be32(par, 0x00000003);
  223. clrbits_be32(par, 0xFFFFFFFC);
  224. break;
  225. }
  226. }
  227. #endif /* #if defined(CONFIG_M5253) */
  228. #if defined(CONFIG_M5271)
  229. void cpu_init_f(void)
  230. {
  231. #ifndef CONFIG_WATCHDOG
  232. /* Disable the watchdog if we aren't using it */
  233. mbar_writeShort(MCF_WTM_WCR, 0);
  234. #endif
  235. /* FlexBus Chipselect */
  236. init_fbcs();
  237. #ifdef CONFIG_SYS_MCF_SYNCR
  238. /* Set clockspeed according to board header file */
  239. mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
  240. #else
  241. /* Set clockspeed to 100MHz */
  242. mbar_writeLong(MCF_FMPLL_SYNCR,
  243. MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
  244. #endif
  245. while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
  246. }
  247. /*
  248. * initialize higher level parts of CPU like timers
  249. */
  250. int cpu_init_r(void)
  251. {
  252. return (0);
  253. }
  254. void uart_port_conf(int port)
  255. {
  256. u16 temp;
  257. /* Setup Ports: */
  258. switch (port) {
  259. case 0:
  260. temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
  261. temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
  262. mbar_writeShort(MCF_GPIO_PAR_UART, temp);
  263. break;
  264. case 1:
  265. temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
  266. temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
  267. mbar_writeShort(MCF_GPIO_PAR_UART, temp);
  268. break;
  269. case 2:
  270. temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
  271. temp |= (0x3000);
  272. mbar_writeShort(MCF_GPIO_PAR_UART, temp);
  273. break;
  274. }
  275. }
  276. #if defined(CONFIG_CMD_NET)
  277. int fecpin_setclear(struct eth_device *dev, int setclear)
  278. {
  279. if (setclear) {
  280. /* Enable Ethernet pins */
  281. mbar_writeByte(MCF_GPIO_PAR_FECI2C,
  282. (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
  283. } else {
  284. }
  285. return 0;
  286. }
  287. #endif /* CONFIG_CMD_NET */
  288. #endif /* CONFIG_M5271 */
  289. #if defined(CONFIG_M5272)
  290. /*
  291. * Breath some life into the CPU...
  292. *
  293. * Set up the memory map,
  294. * initialize a bunch of registers,
  295. * initialize the UPM's
  296. */
  297. void cpu_init_f(void)
  298. {
  299. /* if we come from RAM we assume the CPU is
  300. * already initialized.
  301. */
  302. #ifndef CONFIG_MONITOR_IS_IN_RAM
  303. sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
  304. gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
  305. csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
  306. out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
  307. out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
  308. /* Setup Ports: */
  309. out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
  310. out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
  311. out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
  312. out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
  313. out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
  314. out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
  315. out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
  316. /* Memory Controller: */
  317. out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
  318. out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
  319. #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
  320. out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
  321. out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
  322. #endif
  323. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  324. out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
  325. out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
  326. #endif
  327. #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
  328. out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
  329. out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
  330. #endif
  331. #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
  332. out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
  333. out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
  334. #endif
  335. #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
  336. out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
  337. out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
  338. #endif
  339. #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
  340. out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
  341. out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
  342. #endif
  343. #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
  344. out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
  345. out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
  346. #endif
  347. #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
  348. /* enable instruction cache now */
  349. icache_enable();
  350. }
  351. /*
  352. * initialize higher level parts of CPU like timers
  353. */
  354. int cpu_init_r(void)
  355. {
  356. return (0);
  357. }
  358. void uart_port_conf(int port)
  359. {
  360. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  361. /* Setup Ports: */
  362. switch (port) {
  363. case 0:
  364. clrbits_be32(&gpio->gpio_pbcnt,
  365. GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
  366. setbits_be32(&gpio->gpio_pbcnt,
  367. GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
  368. break;
  369. case 1:
  370. clrbits_be32(&gpio->gpio_pdcnt,
  371. GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
  372. setbits_be32(&gpio->gpio_pdcnt,
  373. GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
  374. break;
  375. }
  376. }
  377. #if defined(CONFIG_CMD_NET)
  378. int fecpin_setclear(struct eth_device *dev, int setclear)
  379. {
  380. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  381. if (setclear) {
  382. setbits_be32(&gpio->gpio_pbcnt,
  383. GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
  384. GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
  385. GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
  386. GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
  387. } else {
  388. }
  389. return 0;
  390. }
  391. #endif /* CONFIG_CMD_NET */
  392. #endif /* #if defined(CONFIG_M5272) */
  393. #if defined(CONFIG_M5275)
  394. /*
  395. * Breathe some life into the CPU...
  396. *
  397. * Set up the memory map,
  398. * initialize a bunch of registers,
  399. * initialize the UPM's
  400. */
  401. void cpu_init_f(void)
  402. {
  403. /*
  404. * if we come from RAM we assume the CPU is
  405. * already initialized.
  406. */
  407. #ifndef CONFIG_MONITOR_IS_IN_RAM
  408. wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
  409. gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
  410. /* Kill watchdog so we can initialize the PLL */
  411. out_be16(&wdog_reg->wcr, 0);
  412. /* FlexBus Chipselect */
  413. init_fbcs();
  414. #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
  415. #ifdef CONFIG_SYS_I2C_FSL
  416. CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
  417. CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
  418. #endif
  419. /* enable instruction cache now */
  420. icache_enable();
  421. }
  422. /*
  423. * initialize higher level parts of CPU like timers
  424. */
  425. int cpu_init_r(void)
  426. {
  427. return (0);
  428. }
  429. void uart_port_conf(int port)
  430. {
  431. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  432. /* Setup Ports: */
  433. switch (port) {
  434. case 0:
  435. clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
  436. setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
  437. break;
  438. case 1:
  439. clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
  440. setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
  441. break;
  442. case 2:
  443. clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
  444. setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
  445. break;
  446. }
  447. }
  448. #if defined(CONFIG_CMD_NET)
  449. int fecpin_setclear(struct eth_device *dev, int setclear)
  450. {
  451. struct fec_info_s *info = (struct fec_info_s *) dev->priv;
  452. gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  453. if (setclear) {
  454. /* Enable Ethernet pins */
  455. if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
  456. setbits_be16(&gpio->par_feci2c, 0x0f00);
  457. setbits_8(&gpio->par_fec0hl, 0xc0);
  458. } else {
  459. setbits_be16(&gpio->par_feci2c, 0x00a0);
  460. setbits_8(&gpio->par_fec1hl, 0xc0);
  461. }
  462. } else {
  463. if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
  464. clrbits_be16(&gpio->par_feci2c, 0x0f00);
  465. clrbits_8(&gpio->par_fec0hl, 0xc0);
  466. } else {
  467. clrbits_be16(&gpio->par_feci2c, 0x00a0);
  468. clrbits_8(&gpio->par_fec1hl, 0xc0);
  469. }
  470. }
  471. return 0;
  472. }
  473. #endif /* CONFIG_CMD_NET */
  474. #endif /* #if defined(CONFIG_M5275) */
  475. #if defined(CONFIG_M5282)
  476. /*
  477. * Breath some life into the CPU...
  478. *
  479. * Set up the memory map,
  480. * initialize a bunch of registers,
  481. * initialize the UPM's
  482. */
  483. void cpu_init_f(void)
  484. {
  485. #ifndef CONFIG_WATCHDOG
  486. /* disable watchdog if we aren't using it */
  487. MCFWTM_WCR = 0;
  488. #endif
  489. #ifndef CONFIG_MONITOR_IS_IN_RAM
  490. /* Set speed /PLL */
  491. MCFCLOCK_SYNCR =
  492. MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
  493. MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
  494. while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
  495. MCFGPIO_PBCDPAR = 0xc0;
  496. /* Set up the GPIO ports */
  497. #ifdef CONFIG_SYS_PEPAR
  498. MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
  499. #endif
  500. #ifdef CONFIG_SYS_PFPAR
  501. MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
  502. #endif
  503. #ifdef CONFIG_SYS_PJPAR
  504. MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
  505. #endif
  506. #ifdef CONFIG_SYS_PSDPAR
  507. MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
  508. #endif
  509. #ifdef CONFIG_SYS_PASPAR
  510. MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
  511. #endif
  512. #ifdef CONFIG_SYS_PEHLPAR
  513. MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
  514. #endif
  515. #ifdef CONFIG_SYS_PQSPAR
  516. MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
  517. #endif
  518. #ifdef CONFIG_SYS_PTCPAR
  519. MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
  520. #endif
  521. #if defined(CONFIG_SYS_PORTTC)
  522. MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
  523. #endif
  524. #if defined(CONFIG_SYS_DDRTC)
  525. MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
  526. #endif
  527. #ifdef CONFIG_SYS_PTDPAR
  528. MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
  529. #endif
  530. #ifdef CONFIG_SYS_PUAPAR
  531. MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
  532. #endif
  533. #if defined(CONFIG_SYS_DDRD)
  534. MCFGPIO_DDRD = CONFIG_SYS_DDRD;
  535. #endif
  536. #ifdef CONFIG_SYS_DDRUA
  537. MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
  538. #endif
  539. /* FlexBus Chipselect */
  540. init_fbcs();
  541. #endif /* CONFIG_MONITOR_IS_IN_RAM */
  542. /* defer enabling cache until boot (see do_go) */
  543. /* icache_enable(); */
  544. }
  545. /*
  546. * initialize higher level parts of CPU like timers
  547. */
  548. int cpu_init_r(void)
  549. {
  550. return (0);
  551. }
  552. void uart_port_conf(int port)
  553. {
  554. /* Setup Ports: */
  555. switch (port) {
  556. case 0:
  557. MCFGPIO_PUAPAR &= 0xFc;
  558. MCFGPIO_PUAPAR |= 0x03;
  559. break;
  560. case 1:
  561. MCFGPIO_PUAPAR &= 0xF3;
  562. MCFGPIO_PUAPAR |= 0x0C;
  563. break;
  564. case 2:
  565. MCFGPIO_PASPAR &= 0xFF0F;
  566. MCFGPIO_PASPAR |= 0x00A0;
  567. break;
  568. }
  569. }
  570. #if defined(CONFIG_CMD_NET)
  571. int fecpin_setclear(struct eth_device *dev, int setclear)
  572. {
  573. if (setclear) {
  574. MCFGPIO_PASPAR |= 0x0F00;
  575. MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
  576. } else {
  577. MCFGPIO_PASPAR &= 0xF0FF;
  578. MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
  579. }
  580. return 0;
  581. }
  582. #endif /* CONFIG_CMD_NET */
  583. #endif
  584. #if defined(CONFIG_M5249)
  585. /*
  586. * Breath some life into the CPU...
  587. *
  588. * Set up the memory map,
  589. * initialize a bunch of registers,
  590. * initialize the UPM's
  591. */
  592. void cpu_init_f(void)
  593. {
  594. /*
  595. * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
  596. * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
  597. * which is their primary function.
  598. * ~Jeremy
  599. */
  600. mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
  601. mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
  602. mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
  603. mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
  604. mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
  605. mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
  606. /*
  607. * dBug Compliance:
  608. * You can verify these values by using dBug's 'ird'
  609. * (Internal Register Display) command
  610. * ~Jeremy
  611. *
  612. */
  613. mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
  614. mbar_writeByte(MCFSIM_SYPCR, 0x00);
  615. mbar_writeByte(MCFSIM_SWIVR, 0x0f);
  616. mbar_writeByte(MCFSIM_SWSR, 0x00);
  617. mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
  618. mbar_writeByte(MCFSIM_SWDICR, 0x00);
  619. mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
  620. mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
  621. mbar_writeByte(MCFSIM_I2CICR, 0x00);
  622. mbar_writeByte(MCFSIM_UART1ICR, 0x00);
  623. mbar_writeByte(MCFSIM_UART2ICR, 0x00);
  624. mbar_writeByte(MCFSIM_ICR6, 0x00);
  625. mbar_writeByte(MCFSIM_ICR7, 0x00);
  626. mbar_writeByte(MCFSIM_ICR8, 0x00);
  627. mbar_writeByte(MCFSIM_ICR9, 0x00);
  628. mbar_writeByte(MCFSIM_QSPIICR, 0x00);
  629. mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
  630. mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
  631. mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
  632. mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
  633. /* Setup interrupt priorities for gpio7 */
  634. /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
  635. /* IDE Config registers */
  636. mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
  637. mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
  638. /* FlexBus Chipselect */
  639. init_fbcs();
  640. /* enable instruction cache now */
  641. icache_enable();
  642. }
  643. /*
  644. * initialize higher level parts of CPU like timers
  645. */
  646. int cpu_init_r(void)
  647. {
  648. return (0);
  649. }
  650. void uart_port_conf(int port)
  651. {
  652. }
  653. #endif /* #if defined(CONFIG_M5249) */