cpu_init.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <watchdog.h>
  13. #include <asm/immap.h>
  14. #include <asm/io.h>
  15. #if defined(CONFIG_CMD_NET)
  16. #include <config.h>
  17. #include <net.h>
  18. #include <asm/fec.h>
  19. #endif
  20. /* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
  21. #ifdef CONFIG_M5235
  22. #define out_be_fbcs_reg out_be16
  23. #else
  24. #define out_be_fbcs_reg out_be32
  25. #endif
  26. /*
  27. * Breath some life into the CPU...
  28. *
  29. * Set up the memory map,
  30. * initialize a bunch of registers,
  31. * initialize the UPM's
  32. */
  33. void cpu_init_f(void)
  34. {
  35. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  36. fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  37. wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  38. scm_t *scm = (scm_t *) MMAP_SCM;
  39. /* watchdog is enabled by default - disable the watchdog */
  40. #ifndef CONFIG_WATCHDOG
  41. out_be16(&wdog->cr, 0);
  42. #endif
  43. out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
  44. /* Port configuration */
  45. out_8(&gpio->par_cs, 0);
  46. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  47. out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  48. out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  49. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  50. #endif
  51. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  52. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
  53. out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  54. out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  55. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  56. #endif
  57. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  58. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
  59. out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  60. out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  61. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  62. #endif
  63. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  64. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
  65. out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  66. out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  67. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  68. #endif
  69. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  70. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
  71. out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  72. out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  73. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  74. #endif
  75. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  76. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
  77. out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  78. out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  79. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  80. #endif
  81. #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
  82. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
  83. out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
  84. out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
  85. out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
  86. #endif
  87. #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
  88. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
  89. out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
  90. out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
  91. out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
  92. #endif
  93. #ifdef CONFIG_SYS_I2C_FSL
  94. CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
  95. CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
  96. #endif
  97. icache_enable();
  98. }
  99. /*
  100. * initialize higher level parts of CPU like timers
  101. */
  102. int cpu_init_r(void)
  103. {
  104. return (0);
  105. }
  106. void uart_port_conf(int port)
  107. {
  108. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  109. /* Setup Ports: */
  110. switch (port) {
  111. case 0:
  112. clrbits_be16(&gpio->par_uart,
  113. GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  114. setbits_be16(&gpio->par_uart,
  115. GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  116. break;
  117. case 1:
  118. clrbits_be16(&gpio->par_uart,
  119. GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
  120. setbits_be16(&gpio->par_uart,
  121. GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
  122. break;
  123. case 2:
  124. #ifdef CONFIG_SYS_UART2_PRI_GPIO
  125. clrbits_be16(&gpio->par_uart,
  126. GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  127. setbits_be16(&gpio->par_uart,
  128. GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  129. #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
  130. clrbits_8(&gpio->par_feci2c,
  131. GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
  132. setbits_8(&gpio->par_feci2c,
  133. GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
  134. #endif
  135. break;
  136. }
  137. }
  138. #if defined(CONFIG_CMD_NET)
  139. int fecpin_setclear(struct eth_device *dev, int setclear)
  140. {
  141. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  142. if (setclear) {
  143. setbits_8(&gpio->par_feci2c,
  144. GPIO_PAR_FECI2C_EMDC_FECEMDC |
  145. GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
  146. } else {
  147. clrbits_8(&gpio->par_feci2c,
  148. GPIO_PAR_FECI2C_EMDC_MASK |
  149. GPIO_PAR_FECI2C_EMDIO_MASK);
  150. }
  151. return 0;
  152. }
  153. #endif