cpu.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <zynqpl.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/ps7_init_gpl.h>
  13. #include <asm/arch/sys_proto.h>
  14. #define ZYNQ_SILICON_VER_MASK 0xF0000000
  15. #define ZYNQ_SILICON_VER_SHIFT 28
  16. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  17. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  18. xilinx_desc fpga = {
  19. .family = xilinx_zynq,
  20. .iface = devcfg,
  21. .operations = &zynq_op,
  22. };
  23. #endif
  24. static const struct {
  25. u8 idcode;
  26. #if defined(CONFIG_FPGA)
  27. u32 fpga_size;
  28. #endif
  29. char *devicename;
  30. } zynq_fpga_descs[] = {
  31. ZYNQ_DESC(7Z007S),
  32. ZYNQ_DESC(7Z010),
  33. ZYNQ_DESC(7Z012S),
  34. ZYNQ_DESC(7Z014S),
  35. ZYNQ_DESC(7Z015),
  36. ZYNQ_DESC(7Z020),
  37. ZYNQ_DESC(7Z030),
  38. ZYNQ_DESC(7Z035),
  39. ZYNQ_DESC(7Z045),
  40. ZYNQ_DESC(7Z100),
  41. { /* Sentinel */ },
  42. };
  43. int arch_cpu_init(void)
  44. {
  45. zynq_slcr_unlock();
  46. #ifndef CONFIG_SPL_BUILD
  47. /* Device config APB, unlock the PCAP */
  48. writel(0x757BDF0D, &devcfg_base->unlock);
  49. writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
  50. #if (CONFIG_SYS_SDRAM_BASE == 0)
  51. /* remap DDR to zero, FILTERSTART */
  52. writel(0, &scu_base->filter_start);
  53. /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
  54. writel(0x1F, &slcr_base->ocm_cfg);
  55. /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
  56. writel(0x0, &slcr_base->fpga_rst_ctrl);
  57. /* Set urgent bits with register */
  58. writel(0x0, &slcr_base->ddr_urgent_sel);
  59. /* Urgent write, ports S2/S3 */
  60. writel(0xC, &slcr_base->ddr_urgent);
  61. #endif
  62. #endif
  63. zynq_slcr_lock();
  64. return 0;
  65. }
  66. unsigned int zynq_get_silicon_version(void)
  67. {
  68. return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
  69. >> ZYNQ_SILICON_VER_SHIFT;
  70. }
  71. void reset_cpu(ulong addr)
  72. {
  73. zynq_slcr_cpu_reset();
  74. while (1)
  75. ;
  76. }
  77. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  78. void enable_caches(void)
  79. {
  80. /* Enable D-cache. I-cache is already enabled in start.S */
  81. dcache_enable();
  82. }
  83. #endif
  84. static int __maybe_unused cpu_desc_id(void)
  85. {
  86. u32 idcode;
  87. u8 i;
  88. idcode = zynq_slcr_get_idcode();
  89. for (i = 0; zynq_fpga_descs[i].idcode; i++) {
  90. if (zynq_fpga_descs[i].idcode == idcode)
  91. return i;
  92. }
  93. return -ENODEV;
  94. }
  95. #if defined(CONFIG_ARCH_EARLY_INIT_R)
  96. int arch_early_init_r(void)
  97. {
  98. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  99. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  100. int cpu_id = cpu_desc_id();
  101. if (cpu_id < 0)
  102. return 0;
  103. fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
  104. fpga.name = zynq_fpga_descs[cpu_id].devicename;
  105. fpga_init();
  106. fpga_add(fpga_xilinx, &fpga);
  107. #endif
  108. return 0;
  109. }
  110. #endif
  111. #ifdef CONFIG_DISPLAY_CPUINFO
  112. int print_cpuinfo(void)
  113. {
  114. u32 version;
  115. int cpu_id = cpu_desc_id();
  116. if (cpu_id < 0)
  117. return 0;
  118. version = zynq_get_silicon_version() << 1;
  119. if (version > (PCW_SILICON_VERSION_3 << 1))
  120. version += 1;
  121. printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
  122. printf("Silicon: v%d.%d\n", version >> 1, version & 1);
  123. return 0;
  124. }
  125. #endif