board.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <ns16550.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  13. #include <asm/arch/clock.h>
  14. #endif
  15. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  16. #include <asm/arch/funcmux.h>
  17. #endif
  18. #if IS_ENABLED(CONFIG_TEGRA_MC)
  19. #include <asm/arch/mc.h>
  20. #endif
  21. #include <asm/arch/tegra.h>
  22. #include <asm/arch-tegra/ap.h>
  23. #include <asm/arch-tegra/board.h>
  24. #include <asm/arch-tegra/cboot.h>
  25. #include <asm/arch-tegra/pmc.h>
  26. #include <asm/arch-tegra/sys_proto.h>
  27. #include <asm/arch-tegra/warmboot.h>
  28. void save_boot_params_ret(void);
  29. DECLARE_GLOBAL_DATA_PTR;
  30. enum {
  31. /* UARTs which we can enable */
  32. UARTA = 1 << 0,
  33. UARTB = 1 << 1,
  34. UARTC = 1 << 2,
  35. UARTD = 1 << 3,
  36. UARTE = 1 << 4,
  37. UART_COUNT = 5,
  38. };
  39. static bool from_spl __attribute__ ((section(".data")));
  40. #ifndef CONFIG_SPL_BUILD
  41. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  42. unsigned long r3)
  43. {
  44. from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  45. /*
  46. * The logic for this is somewhat indirect. The purpose of the marker
  47. * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
  48. * was loaded from a read-only instance of itself, which is something
  49. * that can happen in secure boot setups. So basically the presence
  50. * of the marker is an indication that U-Boot was loaded by one such
  51. * special variant of U-Boot. Conversely, the absence of the marker
  52. * indicates that this instance of U-Boot was loaded by something
  53. * other than a special U-Boot. This could be SPL, but it could just
  54. * as well be one of any number of other first stage bootloaders.
  55. */
  56. if (from_spl)
  57. cboot_save_boot_params(r0, r1, r2, r3);
  58. save_boot_params_ret();
  59. }
  60. #endif
  61. bool spl_was_boot_source(void)
  62. {
  63. return from_spl;
  64. }
  65. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  66. #if !defined(CONFIG_TEGRA124)
  67. #error tegra_cpu_is_non_secure has only been validated on Tegra124
  68. #endif
  69. bool tegra_cpu_is_non_secure(void)
  70. {
  71. /*
  72. * This register reads 0xffffffff in non-secure mode. This register
  73. * only implements bits 31:20, so the lower bits will always read 0 in
  74. * secure mode. Thus, the lower bits are an indicator for secure vs.
  75. * non-secure mode.
  76. */
  77. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  78. uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  79. return (mc_s_cfg0 & 1) == 1;
  80. }
  81. #endif
  82. #if IS_ENABLED(CONFIG_TEGRA_MC)
  83. /* Read the RAM size directly from the memory controller */
  84. static phys_size_t query_sdram_size(void)
  85. {
  86. struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  87. u32 emem_cfg;
  88. phys_size_t size_bytes;
  89. emem_cfg = readl(&mc->mc_emem_cfg);
  90. #if defined(CONFIG_TEGRA20)
  91. debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  92. size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  93. #else
  94. debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  95. #ifndef CONFIG_PHYS_64BIT
  96. /*
  97. * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  98. * and will wrap. Clip the reported size to the maximum that a 32-bit
  99. * variable can represent (rounded to a page).
  100. */
  101. if (emem_cfg >= 4096) {
  102. size_bytes = U32_MAX & ~(0x1000 - 1);
  103. } else
  104. #endif
  105. {
  106. /* RAM size EMC is programmed to. */
  107. size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
  108. #ifndef CONFIG_ARM64
  109. /*
  110. * If all RAM fits within 32-bits, it can be accessed without
  111. * LPAE, so go test the RAM size. Otherwise, we can't access
  112. * all the RAM, and get_ram_size() would get confused, so
  113. * avoid using it. There's no reason we should need this
  114. * validation step anyway.
  115. */
  116. if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  117. size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  118. size_bytes);
  119. #endif
  120. }
  121. #endif
  122. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  123. /* External memory limited to 2047 MB due to IROM/HI-VEC */
  124. if (size_bytes == SZ_2G)
  125. size_bytes -= SZ_1M;
  126. #endif
  127. return size_bytes;
  128. }
  129. #endif
  130. int dram_init(void)
  131. {
  132. int err;
  133. /* try to initialize DRAM from cboot DTB first */
  134. err = cboot_dram_init();
  135. if (err == 0)
  136. return 0;
  137. #if IS_ENABLED(CONFIG_TEGRA_MC)
  138. /* We do not initialise DRAM here. We just query the size */
  139. gd->ram_size = query_sdram_size();
  140. #endif
  141. return 0;
  142. }
  143. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  144. static int uart_configs[] = {
  145. #if defined(CONFIG_TEGRA20)
  146. #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  147. FUNCMUX_UART1_UAA_UAB,
  148. #elif defined(CONFIG_TEGRA_UARTA_GPU)
  149. FUNCMUX_UART1_GPU,
  150. #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  151. FUNCMUX_UART1_SDIO1,
  152. #else
  153. FUNCMUX_UART1_IRRX_IRTX,
  154. #endif
  155. FUNCMUX_UART2_UAD,
  156. -1,
  157. FUNCMUX_UART4_GMC,
  158. -1,
  159. #elif defined(CONFIG_TEGRA30)
  160. FUNCMUX_UART1_ULPI, /* UARTA */
  161. -1,
  162. -1,
  163. -1,
  164. -1,
  165. #elif defined(CONFIG_TEGRA114)
  166. -1,
  167. -1,
  168. -1,
  169. FUNCMUX_UART4_GMI, /* UARTD */
  170. -1,
  171. #elif defined(CONFIG_TEGRA124)
  172. FUNCMUX_UART1_KBC, /* UARTA */
  173. -1,
  174. -1,
  175. FUNCMUX_UART4_GPIO, /* UARTD */
  176. -1,
  177. #else /* Tegra210 */
  178. FUNCMUX_UART1_UART1, /* UARTA */
  179. -1,
  180. -1,
  181. FUNCMUX_UART4_UART4, /* UARTD */
  182. -1,
  183. #endif
  184. };
  185. /**
  186. * Set up the specified uarts
  187. *
  188. * @param uarts_ids Mask containing UARTs to init (UARTx)
  189. */
  190. static void setup_uarts(int uart_ids)
  191. {
  192. static enum periph_id id_for_uart[] = {
  193. PERIPH_ID_UART1,
  194. PERIPH_ID_UART2,
  195. PERIPH_ID_UART3,
  196. PERIPH_ID_UART4,
  197. PERIPH_ID_UART5,
  198. };
  199. size_t i;
  200. for (i = 0; i < UART_COUNT; i++) {
  201. if (uart_ids & (1 << i)) {
  202. enum periph_id id = id_for_uart[i];
  203. funcmux_select(id, uart_configs[i]);
  204. clock_ll_start_uart(id);
  205. }
  206. }
  207. }
  208. #endif
  209. void board_init_uart_f(void)
  210. {
  211. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  212. int uart_ids = 0; /* bit mask of which UART ids to enable */
  213. #ifdef CONFIG_TEGRA_ENABLE_UARTA
  214. uart_ids |= UARTA;
  215. #endif
  216. #ifdef CONFIG_TEGRA_ENABLE_UARTB
  217. uart_ids |= UARTB;
  218. #endif
  219. #ifdef CONFIG_TEGRA_ENABLE_UARTC
  220. uart_ids |= UARTC;
  221. #endif
  222. #ifdef CONFIG_TEGRA_ENABLE_UARTD
  223. uart_ids |= UARTD;
  224. #endif
  225. #ifdef CONFIG_TEGRA_ENABLE_UARTE
  226. uart_ids |= UARTE;
  227. #endif
  228. setup_uarts(uart_ids);
  229. #endif
  230. }
  231. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  232. static struct ns16550_platdata ns16550_com1_pdata = {
  233. .base = CONFIG_SYS_NS16550_COM1,
  234. .reg_shift = 2,
  235. .clock = CONFIG_SYS_NS16550_CLK,
  236. .fcr = UART_FCR_DEFVAL,
  237. };
  238. U_BOOT_DEVICE(ns16550_com1) = {
  239. "ns16550_serial", &ns16550_com1_pdata
  240. };
  241. #endif
  242. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  243. void enable_caches(void)
  244. {
  245. /* Enable D-cache. I-cache is already enabled in start.S */
  246. dcache_enable();
  247. }
  248. #endif