board.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <ram.h>
  10. #include <syscon.h>
  11. #include <asm/io.h>
  12. #include <asm/arch-rockchip/boot_mode.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/periph.h>
  15. #include <asm/arch-rockchip/misc.h>
  16. #include <power/regulator.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. __weak int rk_board_late_init(void)
  19. {
  20. return 0;
  21. }
  22. int board_late_init(void)
  23. {
  24. setup_boot_mode();
  25. return rk_board_late_init();
  26. }
  27. int board_init(void)
  28. {
  29. int ret;
  30. #ifdef CONFIG_DM_REGULATOR
  31. ret = regulators_enable_boot_on(false);
  32. if (ret)
  33. debug("%s: Cannot enable boot on regulator\n", __func__);
  34. #endif
  35. return 0;
  36. }
  37. #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  38. void enable_caches(void)
  39. {
  40. /* Enable D-cache. I-cache is already enabled in start.S */
  41. dcache_enable();
  42. }
  43. #endif
  44. #if defined(CONFIG_USB_GADGET)
  45. #include <usb.h>
  46. #if defined(CONFIG_USB_GADGET_DWC2_OTG)
  47. #include <usb/dwc2_udc.h>
  48. static struct dwc2_plat_otg_data otg_data = {
  49. .rx_fifo_sz = 512,
  50. .np_tx_fifo_sz = 16,
  51. .tx_fifo_sz = 128,
  52. };
  53. int board_usb_init(int index, enum usb_init_type init)
  54. {
  55. ofnode node;
  56. const char *mode;
  57. bool matched = false;
  58. /* find the usb_otg node */
  59. node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
  60. while (ofnode_valid(node)) {
  61. mode = ofnode_read_string(node, "dr_mode");
  62. if (mode && strcmp(mode, "otg") == 0) {
  63. matched = true;
  64. break;
  65. }
  66. node = ofnode_by_compatible(node, "snps,dwc2");
  67. }
  68. if (!matched) {
  69. debug("Not found usb_otg device\n");
  70. return -ENODEV;
  71. }
  72. otg_data.regs_otg = ofnode_get_addr(node);
  73. #ifdef CONFIG_ROCKCHIP_RK3288
  74. int ret;
  75. u32 phandle, offset;
  76. ofnode phy_node;
  77. ret = ofnode_read_u32(node, "phys", &phandle);
  78. if (ret)
  79. return ret;
  80. node = ofnode_get_by_phandle(phandle);
  81. if (!ofnode_valid(node)) {
  82. debug("Not found usb phy device\n");
  83. return -ENODEV;
  84. }
  85. phy_node = ofnode_get_parent(node);
  86. if (!ofnode_valid(node)) {
  87. debug("Not found usb phy device\n");
  88. return -ENODEV;
  89. }
  90. otg_data.phy_of_node = phy_node;
  91. ret = ofnode_read_u32(node, "reg", &offset);
  92. if (ret)
  93. return ret;
  94. otg_data.regs_phy = offset +
  95. (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  96. #endif
  97. return dwc2_udc_probe(&otg_data);
  98. }
  99. int board_usb_cleanup(int index, enum usb_init_type init)
  100. {
  101. return 0;
  102. }
  103. #endif /* CONFIG_USB_GADGET_DWC2_OTG */
  104. #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
  105. #include <dwc3-uboot.h>
  106. static struct dwc3_device dwc3_device_data = {
  107. .maximum_speed = USB_SPEED_HIGH,
  108. .base = 0xfe800000,
  109. .dr_mode = USB_DR_MODE_PERIPHERAL,
  110. .index = 0,
  111. .dis_u2_susphy_quirk = 1,
  112. .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
  113. };
  114. int usb_gadget_handle_interrupts(void)
  115. {
  116. dwc3_uboot_handle_interrupt(0);
  117. return 0;
  118. }
  119. int board_usb_init(int index, enum usb_init_type init)
  120. {
  121. return dwc3_uboot_init(&dwc3_device_data);
  122. }
  123. #endif /* CONFIG_USB_DWC3_GADGET */
  124. #endif /* CONFIG_USB_GADGET */
  125. #if CONFIG_IS_ENABLED(FASTBOOT)
  126. int fastboot_set_reboot_flag(void)
  127. {
  128. printf("Setting reboot to fastboot flag ...\n");
  129. /* Set boot mode to fastboot */
  130. writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
  131. return 0;
  132. }
  133. #endif
  134. #ifdef CONFIG_MISC_INIT_R
  135. __weak int misc_init_r(void)
  136. {
  137. const u32 cpuid_offset = 0x7;
  138. const u32 cpuid_length = 0x10;
  139. u8 cpuid[cpuid_length];
  140. int ret;
  141. ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
  142. if (ret)
  143. return ret;
  144. ret = rockchip_cpuid_set(cpuid, cpuid_length);
  145. if (ret)
  146. return ret;
  147. ret = rockchip_setup_macaddr();
  148. return ret;
  149. }
  150. #endif