memmap-gen3.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas RCar Gen3 memory map tables
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <asm/armv8/mmu.h>
  10. #define GEN3_NR_REGIONS 16
  11. static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
  12. {
  13. .virt = 0x0UL,
  14. .phys = 0x0UL,
  15. .size = 0x40000000UL,
  16. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  17. PTE_BLOCK_NON_SHARE |
  18. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  19. }, {
  20. .virt = 0x40000000UL,
  21. .phys = 0x40000000UL,
  22. .size = 0x03F00000UL,
  23. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24. PTE_BLOCK_INNER_SHARE
  25. }, {
  26. .virt = 0x47E00000UL,
  27. .phys = 0x47E00000UL,
  28. .size = 0x78200000UL,
  29. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  30. PTE_BLOCK_INNER_SHARE
  31. }, {
  32. .virt = 0xc0000000UL,
  33. .phys = 0xc0000000UL,
  34. .size = 0x40000000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  36. PTE_BLOCK_NON_SHARE |
  37. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  38. }, {
  39. .virt = 0x100000000UL,
  40. .phys = 0x100000000UL,
  41. .size = 0xf00000000UL,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  43. PTE_BLOCK_INNER_SHARE
  44. }, {
  45. /* List terminator */
  46. 0,
  47. }
  48. };
  49. struct mm_region *mem_map = gen3_mem_map;
  50. DECLARE_GLOBAL_DATA_PTR;
  51. void enable_caches(void)
  52. {
  53. u64 start, size;
  54. int bank, i = 0;
  55. /* Create map for RPC access */
  56. gen3_mem_map[i].virt = 0x0ULL;
  57. gen3_mem_map[i].phys = 0x0ULL;
  58. gen3_mem_map[i].size = 0x40000000ULL;
  59. gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  60. PTE_BLOCK_NON_SHARE |
  61. PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  62. i++;
  63. /* Generate entires for DRAM in 32bit address space */
  64. for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  65. start = gd->bd->bi_dram[bank].start;
  66. size = gd->bd->bi_dram[bank].size;
  67. /* Skip empty DRAM banks */
  68. if (!size)
  69. continue;
  70. /* Skip DRAM above 4 GiB */
  71. if (start >> 32ULL)
  72. continue;
  73. /* Mark memory reserved by ATF as cacheable too. */
  74. if (start == 0x48000000) {
  75. /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
  76. gen3_mem_map[i].virt = 0x40000000ULL;
  77. gen3_mem_map[i].phys = 0x40000000ULL;
  78. gen3_mem_map[i].size = 0x03F00000ULL;
  79. gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  80. PTE_BLOCK_INNER_SHARE;
  81. i++;
  82. start = 0x47E00000ULL;
  83. size += 0x00200000ULL;
  84. }
  85. gen3_mem_map[i].virt = start;
  86. gen3_mem_map[i].phys = start;
  87. gen3_mem_map[i].size = size;
  88. gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  89. PTE_BLOCK_INNER_SHARE;
  90. i++;
  91. }
  92. /* Create map for register access */
  93. gen3_mem_map[i].virt = 0xc0000000ULL;
  94. gen3_mem_map[i].phys = 0xc0000000ULL;
  95. gen3_mem_map[i].size = 0x40000000ULL;
  96. gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  97. PTE_BLOCK_NON_SHARE |
  98. PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  99. i++;
  100. /* Generate entires for DRAM in 64bit address space */
  101. for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  102. start = gd->bd->bi_dram[bank].start;
  103. size = gd->bd->bi_dram[bank].size;
  104. /* Skip empty DRAM banks */
  105. if (!size)
  106. continue;
  107. /* Skip DRAM below 4 GiB */
  108. if (!(start >> 32ULL))
  109. continue;
  110. gen3_mem_map[i].virt = start;
  111. gen3_mem_map[i].phys = start;
  112. gen3_mem_map[i].size = size;
  113. gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  114. PTE_BLOCK_INNER_SHARE;
  115. i++;
  116. }
  117. /* Zero out the remaining regions. */
  118. for (; i < GEN3_NR_REGIONS; i++) {
  119. gen3_mem_map[i].virt = 0;
  120. gen3_mem_map[i].phys = 0;
  121. gen3_mem_map[i].size = 0;
  122. gen3_mem_map[i].attrs = 0;
  123. }
  124. if (!icache_status())
  125. icache_enable();
  126. dcache_enable();
  127. }