soc.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  17. #error "CPU_TYPE not defined"
  18. #endif
  19. u32 get_cpu_rev(void)
  20. {
  21. #ifdef CONFIG_MX51
  22. int system_rev = 0x51000;
  23. #else
  24. int system_rev = 0x53000;
  25. #endif
  26. int reg = __raw_readl(ROM_SI_REV);
  27. #if defined(CONFIG_MX51)
  28. switch (reg) {
  29. case 0x02:
  30. system_rev |= CHIP_REV_1_1;
  31. break;
  32. case 0x10:
  33. if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  34. system_rev |= CHIP_REV_2_5;
  35. else
  36. system_rev |= CHIP_REV_2_0;
  37. break;
  38. case 0x20:
  39. system_rev |= CHIP_REV_3_0;
  40. break;
  41. default:
  42. system_rev |= CHIP_REV_1_0;
  43. break;
  44. }
  45. #else
  46. if (reg < 0x20)
  47. system_rev |= CHIP_REV_1_0;
  48. else
  49. system_rev |= reg;
  50. #endif
  51. return system_rev;
  52. }
  53. #ifdef CONFIG_REVISION_TAG
  54. u32 __weak get_board_rev(void)
  55. {
  56. return get_cpu_rev();
  57. }
  58. #endif
  59. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  60. void enable_caches(void)
  61. {
  62. /* Enable D-cache. I-cache is already enabled in start.S */
  63. dcache_enable();
  64. }
  65. #endif
  66. #if defined(CONFIG_FEC_MXC)
  67. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  68. {
  69. int i;
  70. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  71. struct fuse_bank *bank = &iim->bank[1];
  72. struct fuse_bank1_regs *fuse =
  73. (struct fuse_bank1_regs *)bank->fuse_regs;
  74. for (i = 0; i < 6; i++)
  75. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  76. }
  77. #endif
  78. #ifdef CONFIG_MX53
  79. void boot_mode_apply(unsigned cfg_val)
  80. {
  81. writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
  82. }
  83. /*
  84. * cfg_val will be used for
  85. * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  86. *
  87. * If bit 28 of LPGR is set upon watchdog reset,
  88. * bits[25:0] of LPGR will move to SBMR.
  89. */
  90. const struct boot_mode soc_boot_modes[] = {
  91. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  92. /* usb or serial download */
  93. {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
  94. {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
  95. {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
  96. {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
  97. {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
  98. {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
  99. /* 4 bit bus width */
  100. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
  101. {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
  102. {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
  103. {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
  104. {NULL, 0},
  105. };
  106. #endif