init.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2012 Stephen Warren
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm/device.h>
  11. #include <fdt_support.h>
  12. #ifdef CONFIG_ARM64
  13. #include <asm/armv8/mmu.h>
  14. static struct mm_region bcm283x_mem_map[] = {
  15. {
  16. .virt = 0x00000000UL,
  17. .phys = 0x00000000UL,
  18. .size = 0x3f000000UL,
  19. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  20. PTE_BLOCK_INNER_SHARE
  21. }, {
  22. .virt = 0x3f000000UL,
  23. .phys = 0x3f000000UL,
  24. .size = 0x01000000UL,
  25. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26. PTE_BLOCK_NON_SHARE |
  27. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  28. }, {
  29. /* List terminator */
  30. 0,
  31. }
  32. };
  33. static struct mm_region bcm2711_mem_map[] = {
  34. {
  35. .virt = 0x00000000UL,
  36. .phys = 0x00000000UL,
  37. .size = 0xfe000000UL,
  38. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  39. PTE_BLOCK_INNER_SHARE
  40. }, {
  41. .virt = 0xfe000000UL,
  42. .phys = 0xfe000000UL,
  43. .size = 0x01800000UL,
  44. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  45. PTE_BLOCK_NON_SHARE |
  46. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  47. }, {
  48. /* List terminator */
  49. 0,
  50. }
  51. };
  52. struct mm_region *mem_map = bcm283x_mem_map;
  53. /*
  54. * I/O address space varies on different chip versions.
  55. * We set the base address by inspecting the DTB.
  56. */
  57. static const struct udevice_id board_ids[] = {
  58. { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
  59. { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
  60. { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
  61. { },
  62. };
  63. static void _rpi_update_mem_map(struct mm_region *pd)
  64. {
  65. int i;
  66. for (i = 0; i < 2; i++) {
  67. mem_map[i].virt = pd[i].virt;
  68. mem_map[i].phys = pd[i].phys;
  69. mem_map[i].size = pd[i].size;
  70. mem_map[i].attrs = pd[i].attrs;
  71. }
  72. }
  73. static void rpi_update_mem_map(void)
  74. {
  75. int ret;
  76. struct mm_region *mm;
  77. const struct udevice_id *of_match = board_ids;
  78. while (of_match->compatible) {
  79. ret = fdt_node_check_compatible(gd->fdt_blob, 0,
  80. of_match->compatible);
  81. if (!ret) {
  82. mm = (struct mm_region *)of_match->data;
  83. _rpi_update_mem_map(mm);
  84. break;
  85. }
  86. of_match++;
  87. }
  88. }
  89. #else
  90. static void rpi_update_mem_map(void) {}
  91. #endif
  92. unsigned long rpi_bcm283x_base = 0x3f000000;
  93. int arch_cpu_init(void)
  94. {
  95. icache_enable();
  96. return 0;
  97. }
  98. int mach_cpu_init(void)
  99. {
  100. int ret, soc_offset;
  101. u64 io_base, size;
  102. rpi_update_mem_map();
  103. /* Get IO base from device tree */
  104. soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
  105. if (soc_offset < 0)
  106. return soc_offset;
  107. ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
  108. &io_base, &size);
  109. if (ret)
  110. return ret;
  111. rpi_bcm283x_base = io_base;
  112. return 0;
  113. }
  114. #ifdef CONFIG_ARMV7_LPAE
  115. void enable_caches(void)
  116. {
  117. dcache_enable();
  118. }
  119. #endif