pxa2xx.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Alex Zuepke <azu@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <asm/arch/pxa-regs.h>
  14. #include <asm/io.h>
  15. #include <asm/system.h>
  16. #include <command.h>
  17. /* Flush I/D-cache */
  18. static void cache_flush(void)
  19. {
  20. unsigned long i = 0;
  21. asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
  22. }
  23. int cleanup_before_linux(void)
  24. {
  25. /*
  26. * This function is called just before we call Linux. It prepares
  27. * the processor for Linux by just disabling everything that can
  28. * disturb booting Linux.
  29. */
  30. disable_interrupts();
  31. icache_disable();
  32. dcache_disable();
  33. cache_flush();
  34. return 0;
  35. }
  36. inline void writelrb(uint32_t val, uint32_t addr)
  37. {
  38. writel(val, addr);
  39. asm volatile("" : : : "memory");
  40. readl(addr);
  41. asm volatile("" : : : "memory");
  42. }
  43. void pxa2xx_dram_init(void)
  44. {
  45. uint32_t tmp;
  46. int i;
  47. /*
  48. * 1) Initialize Asynchronous static memory controller
  49. */
  50. writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
  51. writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
  52. writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
  53. /*
  54. * 2) Initialize Card Interface
  55. */
  56. /* MECR: Memory Expansion Card Register */
  57. writelrb(CONFIG_SYS_MECR_VAL, MECR);
  58. /* MCMEM0: Card Interface slot 0 timing */
  59. writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
  60. /* MCMEM1: Card Interface slot 1 timing */
  61. writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
  62. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  63. writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
  64. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  65. writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
  66. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  67. writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
  68. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  69. writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
  70. /*
  71. * 3) Configure Fly-By DMA register
  72. */
  73. writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
  74. /*
  75. * 4) Initialize Timing for Sync Memory (SDCLK0)
  76. */
  77. /*
  78. * Before accessing MDREFR we need a valid DRI field, so we set
  79. * this to power on defaults + DRI field.
  80. */
  81. /* Read current MDREFR config and zero out DRI */
  82. tmp = readl(MDREFR) & ~0xfff;
  83. /* Add user-specified DRI */
  84. tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
  85. /* Configure important bits */
  86. tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
  87. tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
  88. /* Write MDREFR back */
  89. writelrb(tmp, MDREFR);
  90. /*
  91. * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
  92. */
  93. /* Initialize SXCNFG register. Assert the enable bits.
  94. *
  95. * Write SXMRS to cause an MRS command to all enabled banks of
  96. * synchronous static memory. Note that SXLCR need not be written
  97. * at this time.
  98. */
  99. writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
  100. /*
  101. * 6) Initialize SDRAM
  102. */
  103. writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
  104. writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
  105. /*
  106. * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
  107. * but not enable each SDRAM partition pair.
  108. */
  109. writelrb(CONFIG_SYS_MDCNFG_VAL &
  110. ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
  111. /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
  112. writel(0, OSCR);
  113. while (readl(OSCR) < 0x300)
  114. asm volatile("" : : : "memory");
  115. /*
  116. * 8) Trigger a number (usually 8) refresh cycles by attempting
  117. * non-burst read or write accesses to disabled SDRAM, as commonly
  118. * specified in the power up sequence documented in SDRAM data
  119. * sheets. The address(es) used for this purpose must not be
  120. * cacheable.
  121. */
  122. for (i = 9; i >= 0; i--) {
  123. writel(i, 0xa0000000);
  124. asm volatile("" : : : "memory");
  125. }
  126. /*
  127. * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
  128. */
  129. tmp = CONFIG_SYS_MDCNFG_VAL &
  130. (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
  131. tmp |= readl(MDCNFG);
  132. writelrb(tmp, MDCNFG);
  133. /*
  134. * 10) Write MDMRS.
  135. */
  136. writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
  137. /*
  138. * 11) Enable APD
  139. */
  140. if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
  141. tmp = readl(MDREFR);
  142. tmp |= MDREFR_APD;
  143. writelrb(tmp, MDREFR);
  144. }
  145. }
  146. void pxa_gpio_setup(void)
  147. {
  148. writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
  149. writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
  150. writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
  151. #if defined(CONFIG_CPU_PXA27X)
  152. writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
  153. #endif
  154. writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
  155. writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
  156. writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
  157. #if defined(CONFIG_CPU_PXA27X)
  158. writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
  159. #endif
  160. writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
  161. writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
  162. writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
  163. #if defined(CONFIG_CPU_PXA27X)
  164. writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
  165. #endif
  166. writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
  167. writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
  168. writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
  169. writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
  170. writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
  171. writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
  172. #if defined(CONFIG_CPU_PXA27X)
  173. writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
  174. writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
  175. #endif
  176. writel(CONFIG_SYS_PSSR_VAL, PSSR);
  177. }
  178. void pxa_interrupt_setup(void)
  179. {
  180. writel(0, ICLR);
  181. writel(0, ICMR);
  182. #if defined(CONFIG_CPU_PXA27X)
  183. writel(0, ICLR2);
  184. writel(0, ICMR2);
  185. #endif
  186. }
  187. void pxa_clock_setup(void)
  188. {
  189. writel(CONFIG_SYS_CKEN, CKEN);
  190. writel(CONFIG_SYS_CCCR, CCCR);
  191. asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
  192. /* enable the 32Khz oscillator for RTC and PowerManager */
  193. writel(OSCC_OON, OSCC);
  194. while (!(readl(OSCC) & OSCC_OOK))
  195. asm volatile("" : : : "memory");
  196. }
  197. void pxa_wakeup(void)
  198. {
  199. uint32_t rcsr;
  200. rcsr = readl(RCSR);
  201. writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
  202. /* Wakeup */
  203. if (rcsr & RCSR_SMR) {
  204. writel(PSSR_PH, PSSR);
  205. pxa2xx_dram_init();
  206. icache_disable();
  207. dcache_disable();
  208. asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
  209. }
  210. }
  211. int arch_cpu_init(void)
  212. {
  213. pxa_gpio_setup();
  214. pxa_wakeup();
  215. pxa_interrupt_setup();
  216. pxa_clock_setup();
  217. return 0;
  218. }
  219. void i2c_clk_enable(void)
  220. {
  221. /* Set the global I2C clock on */
  222. writel(readl(CKEN) | CKEN14_I2C, CKEN);
  223. }
  224. void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
  225. void reset_cpu(ulong ignored)
  226. {
  227. uint32_t tmp;
  228. setbits_le32(OWER, OWER_WME);
  229. tmp = readl(OSCR);
  230. tmp += 0x1000;
  231. writel(tmp, OSMR3);
  232. writel(MDREFR_SLFRSH, MDREFR);
  233. for (;;)
  234. ;
  235. }
  236. void enable_caches(void)
  237. {
  238. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  239. icache_enable();
  240. #endif
  241. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  242. dcache_enable();
  243. #endif
  244. }