cache_v8.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. *
  6. * (C) Copyright 2016
  7. * Alexander Graf <agraf@suse.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <asm/system.h>
  12. #include <asm/armv8/mmu.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  15. /*
  16. * With 4k page granule, a virtual address is split into 4 lookup parts
  17. * spanning 9 bits each:
  18. *
  19. * _______________________________________________
  20. * | | | | | | |
  21. * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
  22. * |_______|_______|_______|_______|_______|_______|
  23. * 63-48 47-39 38-30 29-21 20-12 11-00
  24. *
  25. * mask page size
  26. *
  27. * Lv0: FF8000000000 --
  28. * Lv1: 7FC0000000 1G
  29. * Lv2: 3FE00000 2M
  30. * Lv3: 1FF000 4K
  31. * off: FFF
  32. */
  33. u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
  34. {
  35. u64 max_addr = 0;
  36. u64 ips, va_bits;
  37. u64 tcr;
  38. int i;
  39. /* Find the largest address we need to support */
  40. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  41. max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  42. /* Calculate the maximum physical (and thus virtual) address */
  43. if (max_addr > (1ULL << 44)) {
  44. ips = 5;
  45. va_bits = 48;
  46. } else if (max_addr > (1ULL << 42)) {
  47. ips = 4;
  48. va_bits = 44;
  49. } else if (max_addr > (1ULL << 40)) {
  50. ips = 3;
  51. va_bits = 42;
  52. } else if (max_addr > (1ULL << 36)) {
  53. ips = 2;
  54. va_bits = 40;
  55. } else if (max_addr > (1ULL << 32)) {
  56. ips = 1;
  57. va_bits = 36;
  58. } else {
  59. ips = 0;
  60. va_bits = 32;
  61. }
  62. if (el == 1) {
  63. tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  64. } else if (el == 2) {
  65. tcr = TCR_EL2_RSVD | (ips << 16);
  66. } else {
  67. tcr = TCR_EL3_RSVD | (ips << 16);
  68. }
  69. /* PTWs cacheable, inner/outer WBWA and inner shareable */
  70. tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
  71. tcr |= TCR_T0SZ(va_bits);
  72. if (pips)
  73. *pips = ips;
  74. if (pva_bits)
  75. *pva_bits = va_bits;
  76. return tcr;
  77. }
  78. #define MAX_PTE_ENTRIES 512
  79. static int pte_type(u64 *pte)
  80. {
  81. return *pte & PTE_TYPE_MASK;
  82. }
  83. /* Returns the LSB number for a PTE on level <level> */
  84. static int level2shift(int level)
  85. {
  86. /* Page is 12 bits wide, every level translates 9 bits */
  87. return (12 + 9 * (3 - level));
  88. }
  89. static u64 *find_pte(u64 addr, int level)
  90. {
  91. int start_level = 0;
  92. u64 *pte;
  93. u64 idx;
  94. u64 va_bits;
  95. int i;
  96. debug("addr=%llx level=%d\n", addr, level);
  97. get_tcr(0, NULL, &va_bits);
  98. if (va_bits < 39)
  99. start_level = 1;
  100. if (level < start_level)
  101. return NULL;
  102. /* Walk through all page table levels to find our PTE */
  103. pte = (u64*)gd->arch.tlb_addr;
  104. for (i = start_level; i < 4; i++) {
  105. idx = (addr >> level2shift(i)) & 0x1FF;
  106. pte += idx;
  107. debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
  108. /* Found it */
  109. if (i == level)
  110. return pte;
  111. /* PTE is no table (either invalid or block), can't traverse */
  112. if (pte_type(pte) != PTE_TYPE_TABLE)
  113. return NULL;
  114. /* Off to the next level */
  115. pte = (u64*)(*pte & 0x0000fffffffff000ULL);
  116. }
  117. /* Should never reach here */
  118. return NULL;
  119. }
  120. /* Returns and creates a new full table (512 entries) */
  121. static u64 *create_table(void)
  122. {
  123. u64 *new_table = (u64*)gd->arch.tlb_fillptr;
  124. u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
  125. /* Allocate MAX_PTE_ENTRIES pte entries */
  126. gd->arch.tlb_fillptr += pt_len;
  127. if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
  128. panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
  129. "Please increase the size in get_page_table_size()",
  130. gd->arch.tlb_fillptr - gd->arch.tlb_addr,
  131. gd->arch.tlb_size);
  132. /* Mark all entries as invalid */
  133. memset(new_table, 0, pt_len);
  134. return new_table;
  135. }
  136. static void set_pte_table(u64 *pte, u64 *table)
  137. {
  138. /* Point *pte to the new table */
  139. debug("Setting %p to addr=%p\n", pte, table);
  140. *pte = PTE_TYPE_TABLE | (ulong)table;
  141. }
  142. /* Splits a block PTE into table with subpages spanning the old block */
  143. static void split_block(u64 *pte, int level)
  144. {
  145. u64 old_pte = *pte;
  146. u64 *new_table;
  147. u64 i = 0;
  148. /* level describes the parent level, we need the child ones */
  149. int levelshift = level2shift(level + 1);
  150. if (pte_type(pte) != PTE_TYPE_BLOCK)
  151. panic("PTE %p (%llx) is not a block. Some driver code wants to "
  152. "modify dcache settings for an range not covered in "
  153. "mem_map.", pte, old_pte);
  154. new_table = create_table();
  155. debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
  156. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  157. new_table[i] = old_pte | (i << levelshift);
  158. /* Level 3 block PTEs have the table type */
  159. if ((level + 1) == 3)
  160. new_table[i] |= PTE_TYPE_TABLE;
  161. debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
  162. }
  163. /* Set the new table into effect */
  164. set_pte_table(pte, new_table);
  165. }
  166. /* Add one mm_region map entry to the page tables */
  167. static void add_map(struct mm_region *map)
  168. {
  169. u64 *pte;
  170. u64 virt = map->virt;
  171. u64 phys = map->phys;
  172. u64 size = map->size;
  173. u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
  174. u64 blocksize;
  175. int level;
  176. u64 *new_table;
  177. while (size) {
  178. pte = find_pte(virt, 0);
  179. if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
  180. debug("Creating table for virt 0x%llx\n", virt);
  181. new_table = create_table();
  182. set_pte_table(pte, new_table);
  183. }
  184. for (level = 1; level < 4; level++) {
  185. pte = find_pte(virt, level);
  186. if (!pte)
  187. panic("pte not found\n");
  188. blocksize = 1ULL << level2shift(level);
  189. debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
  190. virt, size, blocksize);
  191. if (size >= blocksize && !(virt & (blocksize - 1))) {
  192. /* Page fits, create block PTE */
  193. debug("Setting PTE %p to block virt=%llx\n",
  194. pte, virt);
  195. if (level == 3)
  196. *pte = phys | attrs | PTE_TYPE_PAGE;
  197. else
  198. *pte = phys | attrs;
  199. virt += blocksize;
  200. phys += blocksize;
  201. size -= blocksize;
  202. break;
  203. } else if (pte_type(pte) == PTE_TYPE_FAULT) {
  204. /* Page doesn't fit, create subpages */
  205. debug("Creating subtable for virt 0x%llx blksize=%llx\n",
  206. virt, blocksize);
  207. new_table = create_table();
  208. set_pte_table(pte, new_table);
  209. } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
  210. debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
  211. virt, blocksize);
  212. split_block(pte, level);
  213. }
  214. }
  215. }
  216. }
  217. enum pte_type {
  218. PTE_INVAL,
  219. PTE_BLOCK,
  220. PTE_LEVEL,
  221. };
  222. /*
  223. * This is a recursively called function to count the number of
  224. * page tables we need to cover a particular PTE range. If you
  225. * call this with level = -1 you basically get the full 48 bit
  226. * coverage.
  227. */
  228. static int count_required_pts(u64 addr, int level, u64 maxaddr)
  229. {
  230. int levelshift = level2shift(level);
  231. u64 levelsize = 1ULL << levelshift;
  232. u64 levelmask = levelsize - 1;
  233. u64 levelend = addr + levelsize;
  234. int r = 0;
  235. int i;
  236. enum pte_type pte_type = PTE_INVAL;
  237. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
  238. struct mm_region *map = &mem_map[i];
  239. u64 start = map->virt;
  240. u64 end = start + map->size;
  241. /* Check if the PTE would overlap with the map */
  242. if (max(addr, start) <= min(levelend, end)) {
  243. start = max(addr, start);
  244. end = min(levelend, end);
  245. /* We need a sub-pt for this level */
  246. if ((start & levelmask) || (end & levelmask)) {
  247. pte_type = PTE_LEVEL;
  248. break;
  249. }
  250. /* Lv0 can not do block PTEs, so do levels here too */
  251. if (level <= 0) {
  252. pte_type = PTE_LEVEL;
  253. break;
  254. }
  255. /* PTE is active, but fits into a block */
  256. pte_type = PTE_BLOCK;
  257. }
  258. }
  259. /*
  260. * Block PTEs at this level are already covered by the parent page
  261. * table, so we only need to count sub page tables.
  262. */
  263. if (pte_type == PTE_LEVEL) {
  264. int sublevel = level + 1;
  265. u64 sublevelsize = 1ULL << level2shift(sublevel);
  266. /* Account for the new sub page table ... */
  267. r = 1;
  268. /* ... and for all child page tables that one might have */
  269. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  270. r += count_required_pts(addr, sublevel, maxaddr);
  271. addr += sublevelsize;
  272. if (addr >= maxaddr) {
  273. /*
  274. * We reached the end of address space, no need
  275. * to look any further.
  276. */
  277. break;
  278. }
  279. }
  280. }
  281. return r;
  282. }
  283. /* Returns the estimated required size of all page tables */
  284. __weak u64 get_page_table_size(void)
  285. {
  286. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  287. u64 size = 0;
  288. u64 va_bits;
  289. int start_level = 0;
  290. get_tcr(0, NULL, &va_bits);
  291. if (va_bits < 39)
  292. start_level = 1;
  293. /* Account for all page tables we would need to cover our memory map */
  294. size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
  295. /*
  296. * We need to duplicate our page table once to have an emergency pt to
  297. * resort to when splitting page tables later on
  298. */
  299. size *= 2;
  300. /*
  301. * We may need to split page tables later on if dcache settings change,
  302. * so reserve up to 4 (random pick) page tables for that.
  303. */
  304. size += one_pt * 4;
  305. return size;
  306. }
  307. void setup_pgtables(void)
  308. {
  309. int i;
  310. if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
  311. panic("Page table pointer not setup.");
  312. /*
  313. * Allocate the first level we're on with invalidate entries.
  314. * If the starting level is 0 (va_bits >= 39), then this is our
  315. * Lv0 page table, otherwise it's the entry Lv1 page table.
  316. */
  317. create_table();
  318. /* Now add all MMU table entries one after another to the table */
  319. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  320. add_map(&mem_map[i]);
  321. }
  322. static void setup_all_pgtables(void)
  323. {
  324. u64 tlb_addr = gd->arch.tlb_addr;
  325. u64 tlb_size = gd->arch.tlb_size;
  326. /* Reset the fill ptr */
  327. gd->arch.tlb_fillptr = tlb_addr;
  328. /* Create normal system page tables */
  329. setup_pgtables();
  330. /* Create emergency page tables */
  331. gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
  332. (uintptr_t)gd->arch.tlb_addr;
  333. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  334. setup_pgtables();
  335. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  336. gd->arch.tlb_addr = tlb_addr;
  337. gd->arch.tlb_size = tlb_size;
  338. }
  339. /* to activate the MMU we need to set up virtual memory */
  340. __weak void mmu_setup(void)
  341. {
  342. int el;
  343. /* Set up page tables only once */
  344. if (!gd->arch.tlb_fillptr)
  345. setup_all_pgtables();
  346. el = current_el();
  347. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  348. MEMORY_ATTRIBUTES);
  349. /* enable the mmu */
  350. set_sctlr(get_sctlr() | CR_M);
  351. }
  352. /*
  353. * Performs a invalidation of the entire data cache at all levels
  354. */
  355. void invalidate_dcache_all(void)
  356. {
  357. __asm_invalidate_dcache_all();
  358. __asm_invalidate_l3_dcache();
  359. }
  360. /*
  361. * Performs a clean & invalidation of the entire data cache at all levels.
  362. * This function needs to be inline to avoid using stack.
  363. * __asm_flush_l3_dcache return status of timeout
  364. */
  365. inline void flush_dcache_all(void)
  366. {
  367. int ret;
  368. __asm_flush_dcache_all();
  369. ret = __asm_flush_l3_dcache();
  370. if (ret)
  371. debug("flushing dcache returns 0x%x\n", ret);
  372. else
  373. debug("flushing dcache successfully.\n");
  374. }
  375. #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
  376. /*
  377. * Invalidates range in all levels of D-cache/unified cache
  378. */
  379. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  380. {
  381. __asm_invalidate_dcache_range(start, stop);
  382. }
  383. /*
  384. * Flush range(clean & invalidate) from all levels of D-cache/unified cache
  385. */
  386. void flush_dcache_range(unsigned long start, unsigned long stop)
  387. {
  388. __asm_flush_dcache_range(start, stop);
  389. }
  390. #else
  391. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  392. {
  393. }
  394. void flush_dcache_range(unsigned long start, unsigned long stop)
  395. {
  396. }
  397. #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
  398. void dcache_enable(void)
  399. {
  400. /* The data cache is not active unless the mmu is enabled */
  401. if (!(get_sctlr() & CR_M)) {
  402. invalidate_dcache_all();
  403. __asm_invalidate_tlb_all();
  404. mmu_setup();
  405. }
  406. set_sctlr(get_sctlr() | CR_C);
  407. }
  408. void dcache_disable(void)
  409. {
  410. uint32_t sctlr;
  411. sctlr = get_sctlr();
  412. /* if cache isn't enabled no need to disable */
  413. if (!(sctlr & CR_C))
  414. return;
  415. set_sctlr(sctlr & ~(CR_C|CR_M));
  416. flush_dcache_all();
  417. __asm_invalidate_tlb_all();
  418. }
  419. int dcache_status(void)
  420. {
  421. return (get_sctlr() & CR_C) != 0;
  422. }
  423. u64 *__weak arch_get_page_table(void) {
  424. puts("No page table offset defined\n");
  425. return NULL;
  426. }
  427. static bool is_aligned(u64 addr, u64 size, u64 align)
  428. {
  429. return !(addr & (align - 1)) && !(size & (align - 1));
  430. }
  431. /* Use flag to indicate if attrs has more than d-cache attributes */
  432. static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
  433. {
  434. int levelshift = level2shift(level);
  435. u64 levelsize = 1ULL << levelshift;
  436. u64 *pte = find_pte(start, level);
  437. /* Can we can just modify the current level block PTE? */
  438. if (is_aligned(start, size, levelsize)) {
  439. if (flag) {
  440. *pte &= ~PMD_ATTRMASK;
  441. *pte |= attrs & PMD_ATTRMASK;
  442. } else {
  443. *pte &= ~PMD_ATTRINDX_MASK;
  444. *pte |= attrs & PMD_ATTRINDX_MASK;
  445. }
  446. debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
  447. return levelsize;
  448. }
  449. /* Unaligned or doesn't fit, maybe split block into table */
  450. debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
  451. /* Maybe we need to split the block into a table */
  452. if (pte_type(pte) == PTE_TYPE_BLOCK)
  453. split_block(pte, level);
  454. /* And then double-check it became a table or already is one */
  455. if (pte_type(pte) != PTE_TYPE_TABLE)
  456. panic("PTE %p (%llx) for addr=%llx should be a table",
  457. pte, *pte, start);
  458. /* Roll on to the next page table level */
  459. return 0;
  460. }
  461. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  462. enum dcache_option option)
  463. {
  464. u64 attrs = PMD_ATTRINDX(option);
  465. u64 real_start = start;
  466. u64 real_size = size;
  467. debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
  468. if (!gd->arch.tlb_emerg)
  469. panic("Emergency page table not setup.");
  470. /*
  471. * We can not modify page tables that we're currently running on,
  472. * so we first need to switch to the "emergency" page tables where
  473. * we can safely modify our primary page tables and then switch back
  474. */
  475. __asm_switch_ttbr(gd->arch.tlb_emerg);
  476. /*
  477. * Loop through the address range until we find a page granule that fits
  478. * our alignment constraints, then set it to the new cache attributes
  479. */
  480. while (size > 0) {
  481. int level;
  482. u64 r;
  483. for (level = 1; level < 4; level++) {
  484. /* Set d-cache attributes only */
  485. r = set_one_region(start, size, attrs, false, level);
  486. if (r) {
  487. /* PTE successfully replaced */
  488. size -= r;
  489. start += r;
  490. break;
  491. }
  492. }
  493. }
  494. /* We're done modifying page tables, switch back to our primary ones */
  495. __asm_switch_ttbr(gd->arch.tlb_addr);
  496. /*
  497. * Make sure there's nothing stale in dcache for a region that might
  498. * have caches off now
  499. */
  500. flush_dcache_range(real_start, real_start + real_size);
  501. }
  502. /*
  503. * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
  504. * The procecess is break-before-make. The target region will be marked as
  505. * invalid during the process of changing.
  506. */
  507. void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
  508. {
  509. int level;
  510. u64 r, size, start;
  511. start = addr;
  512. size = siz;
  513. /*
  514. * Loop through the address range until we find a page granule that fits
  515. * our alignment constraints, then set it to "invalid".
  516. */
  517. while (size > 0) {
  518. for (level = 1; level < 4; level++) {
  519. /* Set PTE to fault */
  520. r = set_one_region(start, size, PTE_TYPE_FAULT, true,
  521. level);
  522. if (r) {
  523. /* PTE successfully invalidated */
  524. size -= r;
  525. start += r;
  526. break;
  527. }
  528. }
  529. }
  530. flush_dcache_range(gd->arch.tlb_addr,
  531. gd->arch.tlb_addr + gd->arch.tlb_size);
  532. __asm_invalidate_tlb_all();
  533. /*
  534. * Loop through the address range until we find a page granule that fits
  535. * our alignment constraints, then set it to the new cache attributes
  536. */
  537. start = addr;
  538. size = siz;
  539. while (size > 0) {
  540. for (level = 1; level < 4; level++) {
  541. /* Set PTE to new attributes */
  542. r = set_one_region(start, size, attrs, true, level);
  543. if (r) {
  544. /* PTE successfully updated */
  545. size -= r;
  546. start += r;
  547. break;
  548. }
  549. }
  550. }
  551. flush_dcache_range(gd->arch.tlb_addr,
  552. gd->arch.tlb_addr + gd->arch.tlb_size);
  553. __asm_invalidate_tlb_all();
  554. }
  555. #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  556. /*
  557. * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
  558. * running however really wants to have dcache and the MMU active. Check that
  559. * everything is sane and give the developer a hint if it isn't.
  560. */
  561. #ifndef CONFIG_SPL_BUILD
  562. #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
  563. #endif
  564. void invalidate_dcache_all(void)
  565. {
  566. }
  567. void flush_dcache_all(void)
  568. {
  569. }
  570. void dcache_enable(void)
  571. {
  572. }
  573. void dcache_disable(void)
  574. {
  575. }
  576. int dcache_status(void)
  577. {
  578. return 0;
  579. }
  580. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  581. enum dcache_option option)
  582. {
  583. }
  584. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  585. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  586. void icache_enable(void)
  587. {
  588. invalidate_icache_all();
  589. set_sctlr(get_sctlr() | CR_I);
  590. }
  591. void icache_disable(void)
  592. {
  593. set_sctlr(get_sctlr() & ~CR_I);
  594. }
  595. int icache_status(void)
  596. {
  597. return (get_sctlr() & CR_I) != 0;
  598. }
  599. void invalidate_icache_all(void)
  600. {
  601. __asm_invalidate_icache_all();
  602. __asm_invalidate_l3_icache();
  603. }
  604. #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  605. void icache_enable(void)
  606. {
  607. }
  608. void icache_disable(void)
  609. {
  610. }
  611. int icache_status(void)
  612. {
  613. return 0;
  614. }
  615. void invalidate_icache_all(void)
  616. {
  617. }
  618. #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  619. /*
  620. * Enable dCache & iCache, whether cache is actually enabled
  621. * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  622. */
  623. void __weak enable_caches(void)
  624. {
  625. icache_enable();
  626. dcache_enable();
  627. }