cpu.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/armada100.h>
  12. #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
  13. #define SET_MRVL_ID (1<<8)
  14. #define L2C_RAM_SEL (1<<4)
  15. int arch_cpu_init(void)
  16. {
  17. u32 val;
  18. struct armd1cpu_registers *cpuregs =
  19. (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  20. struct armd1apb1_registers *apb1clkres =
  21. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  22. struct armd1mpmu_registers *mpmu =
  23. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  24. /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
  25. val = readl(&cpuregs->cpu_conf);
  26. val = val | SET_MRVL_ID;
  27. writel(val, &cpuregs->cpu_conf);
  28. /* Enable Clocks for all hardware units */
  29. writel(0xFFFFFFFF, &mpmu->acgr);
  30. /* Turn on AIB and AIB-APB Functional clock */
  31. writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
  32. /* ensure L2 cache is not mapped as SRAM */
  33. val = readl(&cpuregs->cpu_conf);
  34. val = val & ~(L2C_RAM_SEL);
  35. writel(val, &cpuregs->cpu_conf);
  36. /* Enable GPIO clock */
  37. writel(APBC_APBCLK, &apb1clkres->gpio);
  38. #ifdef CONFIG_I2C_MV
  39. /* Enable general I2C clock */
  40. writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  41. writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  42. /* Enable power I2C clock */
  43. writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  44. writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  45. #endif
  46. /*
  47. * Enable Functional and APB clock at 14.7456MHz
  48. * for configured UART console
  49. */
  50. #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
  51. writel(UARTCLK14745KHZ, &apb1clkres->uart3);
  52. #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
  53. writel(UARTCLK14745KHZ, &apb1clkres->uart2);
  54. #else
  55. writel(UARTCLK14745KHZ, &apb1clkres->uart1);
  56. #endif
  57. icache_enable();
  58. return 0;
  59. }
  60. #if defined(CONFIG_DISPLAY_CPUINFO)
  61. int print_cpuinfo(void)
  62. {
  63. u32 id;
  64. struct armd1cpu_registers *cpuregs =
  65. (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  66. id = readl(&cpuregs->chip_id);
  67. printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
  68. return 0;
  69. }
  70. #endif
  71. #ifdef CONFIG_I2C_MV
  72. void i2c_clk_enable(void)
  73. {
  74. }
  75. #endif