core.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11. * to uboot.
  12. *
  13. * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <malloc.h>
  18. #include <dwc3-uboot.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/devres.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/err.h>
  23. #include <linux/ioport.h>
  24. #include <dm.h>
  25. #include <generic-phy.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include "core.h"
  29. #include "gadget.h"
  30. #include "io.h"
  31. #include "linux-compat.h"
  32. static LIST_HEAD(dwc3_list);
  33. /* -------------------------------------------------------------------------- */
  34. static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  35. {
  36. u32 reg;
  37. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  38. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  39. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  40. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  41. }
  42. /**
  43. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  44. * @dwc: pointer to our context structure
  45. */
  46. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  47. {
  48. u32 reg;
  49. /* Before Resetting PHY, put Core in Reset */
  50. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  51. reg |= DWC3_GCTL_CORESOFTRESET;
  52. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  53. /* Assert USB3 PHY reset */
  54. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  55. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  56. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  57. /* Assert USB2 PHY reset */
  58. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  59. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  60. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  61. mdelay(100);
  62. /* Clear USB3 PHY reset */
  63. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  64. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  65. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  66. /* Clear USB2 PHY reset */
  67. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  68. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  69. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  70. mdelay(100);
  71. /* After PHYs are stable we can take Core out of reset state */
  72. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  73. reg &= ~DWC3_GCTL_CORESOFTRESET;
  74. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  75. return 0;
  76. }
  77. /**
  78. * dwc3_free_one_event_buffer - Frees one event buffer
  79. * @dwc: Pointer to our controller context structure
  80. * @evt: Pointer to event buffer to be freed
  81. */
  82. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  83. struct dwc3_event_buffer *evt)
  84. {
  85. dma_free_coherent(evt->buf);
  86. }
  87. /**
  88. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  89. * @dwc: Pointer to our controller context structure
  90. * @length: size of the event buffer
  91. *
  92. * Returns a pointer to the allocated event buffer structure on success
  93. * otherwise ERR_PTR(errno).
  94. */
  95. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  96. unsigned length)
  97. {
  98. struct dwc3_event_buffer *evt;
  99. evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
  100. GFP_KERNEL);
  101. if (!evt)
  102. return ERR_PTR(-ENOMEM);
  103. evt->dwc = dwc;
  104. evt->length = length;
  105. evt->buf = dma_alloc_coherent(length,
  106. (unsigned long *)&evt->dma);
  107. if (!evt->buf)
  108. return ERR_PTR(-ENOMEM);
  109. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  110. return evt;
  111. }
  112. /**
  113. * dwc3_free_event_buffers - frees all allocated event buffers
  114. * @dwc: Pointer to our controller context structure
  115. */
  116. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  117. {
  118. struct dwc3_event_buffer *evt;
  119. int i;
  120. for (i = 0; i < dwc->num_event_buffers; i++) {
  121. evt = dwc->ev_buffs[i];
  122. if (evt)
  123. dwc3_free_one_event_buffer(dwc, evt);
  124. }
  125. }
  126. /**
  127. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  128. * @dwc: pointer to our controller context structure
  129. * @length: size of event buffer
  130. *
  131. * Returns 0 on success otherwise negative errno. In the error case, dwc
  132. * may contain some buffers allocated but not all which were requested.
  133. */
  134. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  135. {
  136. int num;
  137. int i;
  138. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  139. dwc->num_event_buffers = num;
  140. dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
  141. sizeof(*dwc->ev_buffs) * num);
  142. if (!dwc->ev_buffs)
  143. return -ENOMEM;
  144. for (i = 0; i < num; i++) {
  145. struct dwc3_event_buffer *evt;
  146. evt = dwc3_alloc_one_event_buffer(dwc, length);
  147. if (IS_ERR(evt)) {
  148. dev_err(dwc->dev, "can't allocate event buffer\n");
  149. return PTR_ERR(evt);
  150. }
  151. dwc->ev_buffs[i] = evt;
  152. }
  153. return 0;
  154. }
  155. /**
  156. * dwc3_event_buffers_setup - setup our allocated event buffers
  157. * @dwc: pointer to our controller context structure
  158. *
  159. * Returns 0 on success otherwise negative errno.
  160. */
  161. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  162. {
  163. struct dwc3_event_buffer *evt;
  164. int n;
  165. for (n = 0; n < dwc->num_event_buffers; n++) {
  166. evt = dwc->ev_buffs[n];
  167. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  168. evt->buf, (unsigned long long) evt->dma,
  169. evt->length);
  170. evt->lpos = 0;
  171. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  172. lower_32_bits(evt->dma));
  173. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  174. upper_32_bits(evt->dma));
  175. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  176. DWC3_GEVNTSIZ_SIZE(evt->length));
  177. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  178. }
  179. return 0;
  180. }
  181. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  182. {
  183. struct dwc3_event_buffer *evt;
  184. int n;
  185. for (n = 0; n < dwc->num_event_buffers; n++) {
  186. evt = dwc->ev_buffs[n];
  187. evt->lpos = 0;
  188. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  189. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  190. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
  191. | DWC3_GEVNTSIZ_SIZE(0));
  192. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  193. }
  194. }
  195. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  196. {
  197. if (!dwc->has_hibernation)
  198. return 0;
  199. if (!dwc->nr_scratch)
  200. return 0;
  201. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  202. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  203. if (!dwc->scratchbuf)
  204. return -ENOMEM;
  205. return 0;
  206. }
  207. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  208. {
  209. dma_addr_t scratch_addr;
  210. u32 param;
  211. int ret;
  212. if (!dwc->has_hibernation)
  213. return 0;
  214. if (!dwc->nr_scratch)
  215. return 0;
  216. scratch_addr = dma_map_single(dwc->scratchbuf,
  217. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  218. DMA_BIDIRECTIONAL);
  219. if (dma_mapping_error(dwc->dev, scratch_addr)) {
  220. dev_err(dwc->dev, "failed to map scratch buffer\n");
  221. ret = -EFAULT;
  222. goto err0;
  223. }
  224. dwc->scratch_addr = scratch_addr;
  225. param = lower_32_bits(scratch_addr);
  226. ret = dwc3_send_gadget_generic_command(dwc,
  227. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  228. if (ret < 0)
  229. goto err1;
  230. param = upper_32_bits(scratch_addr);
  231. ret = dwc3_send_gadget_generic_command(dwc,
  232. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  233. if (ret < 0)
  234. goto err1;
  235. return 0;
  236. err1:
  237. dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  238. DMA_BIDIRECTIONAL);
  239. err0:
  240. return ret;
  241. }
  242. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  243. {
  244. if (!dwc->has_hibernation)
  245. return;
  246. if (!dwc->nr_scratch)
  247. return;
  248. dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
  249. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  250. kfree(dwc->scratchbuf);
  251. }
  252. static void dwc3_core_num_eps(struct dwc3 *dwc)
  253. {
  254. struct dwc3_hwparams *parms = &dwc->hwparams;
  255. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  256. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  257. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  258. dwc->num_in_eps, dwc->num_out_eps);
  259. }
  260. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  261. {
  262. struct dwc3_hwparams *parms = &dwc->hwparams;
  263. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  264. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  265. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  266. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  267. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  268. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  269. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  270. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  271. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  272. }
  273. /**
  274. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  275. * @dwc: Pointer to our controller context structure
  276. */
  277. static void dwc3_phy_setup(struct dwc3 *dwc)
  278. {
  279. u32 reg;
  280. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  281. /*
  282. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  283. * to '0' during coreConsultant configuration. So default value
  284. * will be '0' when the core is reset. Application needs to set it
  285. * to '1' after the core initialization is completed.
  286. */
  287. if (dwc->revision > DWC3_REVISION_194A)
  288. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  289. if (dwc->u2ss_inp3_quirk)
  290. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  291. if (dwc->req_p1p2p3_quirk)
  292. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  293. if (dwc->del_p1p2p3_quirk)
  294. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  295. if (dwc->del_phy_power_chg_quirk)
  296. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  297. if (dwc->lfps_filter_quirk)
  298. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  299. if (dwc->rx_detect_poll_quirk)
  300. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  301. if (dwc->tx_de_emphasis_quirk)
  302. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  303. if (dwc->dis_u3_susphy_quirk)
  304. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  305. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  306. mdelay(100);
  307. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  308. /*
  309. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  310. * '0' during coreConsultant configuration. So default value will
  311. * be '0' when the core is reset. Application needs to set it to
  312. * '1' after the core initialization is completed.
  313. */
  314. if (dwc->revision > DWC3_REVISION_194A)
  315. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  316. if (dwc->dis_u2_susphy_quirk)
  317. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  318. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  319. mdelay(100);
  320. }
  321. /**
  322. * dwc3_core_init - Low-level initialization of DWC3 Core
  323. * @dwc: Pointer to our controller context structure
  324. *
  325. * Returns 0 on success otherwise negative errno.
  326. */
  327. static int dwc3_core_init(struct dwc3 *dwc)
  328. {
  329. unsigned long timeout;
  330. u32 hwparams4 = dwc->hwparams.hwparams4;
  331. u32 reg;
  332. int ret;
  333. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  334. /* This should read as U3 followed by revision number */
  335. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  336. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  337. ret = -ENODEV;
  338. goto err0;
  339. }
  340. dwc->revision = reg;
  341. /* Handle USB2.0-only core configuration */
  342. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  343. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  344. if (dwc->maximum_speed == USB_SPEED_SUPER)
  345. dwc->maximum_speed = USB_SPEED_HIGH;
  346. }
  347. /* issue device SoftReset too */
  348. timeout = 5000;
  349. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  350. while (timeout--) {
  351. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  352. if (!(reg & DWC3_DCTL_CSFTRST))
  353. break;
  354. };
  355. if (!timeout) {
  356. dev_err(dwc->dev, "Reset Timed Out\n");
  357. ret = -ETIMEDOUT;
  358. goto err0;
  359. }
  360. dwc3_phy_setup(dwc);
  361. ret = dwc3_core_soft_reset(dwc);
  362. if (ret)
  363. goto err0;
  364. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  365. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  366. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  367. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  368. /**
  369. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  370. * issue which would cause xHCI compliance tests to fail.
  371. *
  372. * Because of that we cannot enable clock gating on such
  373. * configurations.
  374. *
  375. * Refers to:
  376. *
  377. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  378. * SOF/ITP Mode Used
  379. */
  380. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  381. dwc->dr_mode == USB_DR_MODE_OTG) &&
  382. (dwc->revision >= DWC3_REVISION_210A &&
  383. dwc->revision <= DWC3_REVISION_250A))
  384. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  385. else
  386. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  387. break;
  388. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  389. /* enable hibernation here */
  390. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  391. /*
  392. * REVISIT Enabling this bit so that host-mode hibernation
  393. * will work. Device-mode hibernation is not yet implemented.
  394. */
  395. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  396. break;
  397. default:
  398. dev_dbg(dwc->dev, "No power optimization available\n");
  399. }
  400. /* check if current dwc3 is on simulation board */
  401. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  402. dev_dbg(dwc->dev, "it is on FPGA board\n");
  403. dwc->is_fpga = true;
  404. }
  405. if(dwc->disable_scramble_quirk && !dwc->is_fpga)
  406. WARN(true,
  407. "disable_scramble cannot be used on non-FPGA builds\n");
  408. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  409. reg |= DWC3_GCTL_DISSCRAMBLE;
  410. else
  411. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  412. if (dwc->u2exit_lfps_quirk)
  413. reg |= DWC3_GCTL_U2EXIT_LFPS;
  414. /*
  415. * WORKAROUND: DWC3 revisions <1.90a have a bug
  416. * where the device can fail to connect at SuperSpeed
  417. * and falls back to high-speed mode which causes
  418. * the device to enter a Connect/Disconnect loop
  419. */
  420. if (dwc->revision < DWC3_REVISION_190A)
  421. reg |= DWC3_GCTL_U2RSTECN;
  422. dwc3_core_num_eps(dwc);
  423. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  424. ret = dwc3_alloc_scratch_buffers(dwc);
  425. if (ret)
  426. goto err0;
  427. ret = dwc3_setup_scratch_buffers(dwc);
  428. if (ret)
  429. goto err1;
  430. return 0;
  431. err1:
  432. dwc3_free_scratch_buffers(dwc);
  433. err0:
  434. return ret;
  435. }
  436. static void dwc3_core_exit(struct dwc3 *dwc)
  437. {
  438. dwc3_free_scratch_buffers(dwc);
  439. }
  440. static int dwc3_core_init_mode(struct dwc3 *dwc)
  441. {
  442. int ret;
  443. switch (dwc->dr_mode) {
  444. case USB_DR_MODE_PERIPHERAL:
  445. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  446. ret = dwc3_gadget_init(dwc);
  447. if (ret) {
  448. dev_err(dev, "failed to initialize gadget\n");
  449. return ret;
  450. }
  451. break;
  452. case USB_DR_MODE_HOST:
  453. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  454. ret = dwc3_host_init(dwc);
  455. if (ret) {
  456. dev_err(dev, "failed to initialize host\n");
  457. return ret;
  458. }
  459. break;
  460. case USB_DR_MODE_OTG:
  461. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  462. ret = dwc3_host_init(dwc);
  463. if (ret) {
  464. dev_err(dev, "failed to initialize host\n");
  465. return ret;
  466. }
  467. ret = dwc3_gadget_init(dwc);
  468. if (ret) {
  469. dev_err(dev, "failed to initialize gadget\n");
  470. return ret;
  471. }
  472. break;
  473. default:
  474. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  475. return -EINVAL;
  476. }
  477. return 0;
  478. }
  479. static void dwc3_gadget_run(struct dwc3 *dwc)
  480. {
  481. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
  482. mdelay(100);
  483. }
  484. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  485. {
  486. switch (dwc->dr_mode) {
  487. case USB_DR_MODE_PERIPHERAL:
  488. dwc3_gadget_exit(dwc);
  489. break;
  490. case USB_DR_MODE_HOST:
  491. dwc3_host_exit(dwc);
  492. break;
  493. case USB_DR_MODE_OTG:
  494. dwc3_host_exit(dwc);
  495. dwc3_gadget_exit(dwc);
  496. break;
  497. default:
  498. /* do nothing */
  499. break;
  500. }
  501. /*
  502. * switch back to peripheral mode
  503. * This enables the phy to enter idle and then, if enabled, suspend.
  504. */
  505. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  506. dwc3_gadget_run(dwc);
  507. }
  508. static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
  509. struct dwc3 *dwc)
  510. {
  511. enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
  512. u32 reg;
  513. /* Set dwc3 usb2 phy config */
  514. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  515. switch (hsphy_mode) {
  516. case USBPHY_INTERFACE_MODE_UTMI:
  517. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  518. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  519. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  520. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  521. break;
  522. case USBPHY_INTERFACE_MODE_UTMIW:
  523. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  524. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  525. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  526. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  527. break;
  528. default:
  529. break;
  530. }
  531. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  532. }
  533. #define DWC3_ALIGN_MASK (16 - 1)
  534. /**
  535. * dwc3_uboot_init - dwc3 core uboot initialization code
  536. * @dwc3_dev: struct dwc3_device containing initialization data
  537. *
  538. * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
  539. * kernel driver). Pointer to dwc3_device should be passed containing
  540. * base address and other initialization data. Returns '0' on success and
  541. * a negative value on failure.
  542. *
  543. * Generally called from board_usb_init() implemented in board file.
  544. */
  545. int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
  546. {
  547. struct dwc3 *dwc;
  548. struct device *dev = NULL;
  549. u8 lpm_nyet_threshold;
  550. u8 tx_de_emphasis;
  551. u8 hird_threshold;
  552. int ret;
  553. void *mem;
  554. mem = devm_kzalloc((struct udevice *)dev,
  555. sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  556. if (!mem)
  557. return -ENOMEM;
  558. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  559. dwc->mem = mem;
  560. dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
  561. DWC3_GLOBALS_REGS_START);
  562. /* default to highest possible threshold */
  563. lpm_nyet_threshold = 0xff;
  564. /* default to -3.5dB de-emphasis */
  565. tx_de_emphasis = 1;
  566. /*
  567. * default to assert utmi_sleep_n and use maximum allowed HIRD
  568. * threshold value of 0b1100
  569. */
  570. hird_threshold = 12;
  571. dwc->maximum_speed = dwc3_dev->maximum_speed;
  572. dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
  573. if (dwc3_dev->lpm_nyet_threshold)
  574. lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
  575. dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
  576. if (dwc3_dev->hird_threshold)
  577. hird_threshold = dwc3_dev->hird_threshold;
  578. dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
  579. dwc->dr_mode = dwc3_dev->dr_mode;
  580. dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
  581. dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
  582. dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
  583. dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
  584. dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
  585. dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
  586. dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
  587. dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
  588. dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
  589. dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
  590. dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
  591. if (dwc3_dev->tx_de_emphasis)
  592. tx_de_emphasis = dwc3_dev->tx_de_emphasis;
  593. /* default to superspeed if no maximum_speed passed */
  594. if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
  595. dwc->maximum_speed = USB_SPEED_SUPER;
  596. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  597. dwc->tx_de_emphasis = tx_de_emphasis;
  598. dwc->hird_threshold = hird_threshold
  599. | (dwc->is_utmi_l1_suspend << 4);
  600. dwc->index = dwc3_dev->index;
  601. dwc3_cache_hwparams(dwc);
  602. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  603. if (ret) {
  604. dev_err(dwc->dev, "failed to allocate event buffers\n");
  605. return -ENOMEM;
  606. }
  607. if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  608. dwc->dr_mode = USB_DR_MODE_HOST;
  609. else if (!IS_ENABLED(CONFIG_USB_HOST))
  610. dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
  611. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  612. dwc->dr_mode = USB_DR_MODE_OTG;
  613. ret = dwc3_core_init(dwc);
  614. if (ret) {
  615. dev_err(dev, "failed to initialize core\n");
  616. goto err0;
  617. }
  618. dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
  619. ret = dwc3_event_buffers_setup(dwc);
  620. if (ret) {
  621. dev_err(dwc->dev, "failed to setup event buffers\n");
  622. goto err1;
  623. }
  624. ret = dwc3_core_init_mode(dwc);
  625. if (ret)
  626. goto err2;
  627. list_add_tail(&dwc->list, &dwc3_list);
  628. return 0;
  629. err2:
  630. dwc3_event_buffers_cleanup(dwc);
  631. err1:
  632. dwc3_core_exit(dwc);
  633. err0:
  634. dwc3_free_event_buffers(dwc);
  635. return ret;
  636. }
  637. /**
  638. * dwc3_uboot_exit - dwc3 core uboot cleanup code
  639. * @index: index of this controller
  640. *
  641. * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
  642. * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
  643. * should be passed and should match with the index passed in
  644. * dwc3_device during init.
  645. *
  646. * Generally called from board file.
  647. */
  648. void dwc3_uboot_exit(int index)
  649. {
  650. struct dwc3 *dwc;
  651. list_for_each_entry(dwc, &dwc3_list, list) {
  652. if (dwc->index != index)
  653. continue;
  654. dwc3_core_exit_mode(dwc);
  655. dwc3_event_buffers_cleanup(dwc);
  656. dwc3_free_event_buffers(dwc);
  657. dwc3_core_exit(dwc);
  658. list_del(&dwc->list);
  659. kfree(dwc->mem);
  660. break;
  661. }
  662. }
  663. /**
  664. * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
  665. * @index: index of this controller
  666. *
  667. * Invokes dwc3 gadget interrupts.
  668. *
  669. * Generally called from board file.
  670. */
  671. void dwc3_uboot_handle_interrupt(int index)
  672. {
  673. struct dwc3 *dwc = NULL;
  674. list_for_each_entry(dwc, &dwc3_list, list) {
  675. if (dwc->index != index)
  676. continue;
  677. dwc3_gadget_uboot_handle_interrupt(dwc);
  678. break;
  679. }
  680. }
  681. MODULE_ALIAS("platform:dwc3");
  682. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  683. MODULE_LICENSE("GPL v2");
  684. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  685. #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
  686. int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
  687. {
  688. int i, ret, count;
  689. struct phy *usb_phys;
  690. /* Return if no phy declared */
  691. if (!dev_read_prop(dev, "phys", NULL))
  692. return 0;
  693. count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
  694. if (count <= 0)
  695. return count;
  696. usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
  697. GFP_KERNEL);
  698. if (!usb_phys)
  699. return -ENOMEM;
  700. for (i = 0; i < count; i++) {
  701. ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
  702. if (ret && ret != -ENOENT) {
  703. pr_err("Failed to get USB PHY%d for %s\n",
  704. i, dev->name);
  705. return ret;
  706. }
  707. }
  708. for (i = 0; i < count; i++) {
  709. ret = generic_phy_init(&usb_phys[i]);
  710. if (ret) {
  711. pr_err("Can't init USB PHY%d for %s\n",
  712. i, dev->name);
  713. goto phys_init_err;
  714. }
  715. }
  716. for (i = 0; i < count; i++) {
  717. ret = generic_phy_power_on(&usb_phys[i]);
  718. if (ret) {
  719. pr_err("Can't power USB PHY%d for %s\n",
  720. i, dev->name);
  721. goto phys_poweron_err;
  722. }
  723. }
  724. *array = usb_phys;
  725. *num_phys = count;
  726. return 0;
  727. phys_poweron_err:
  728. for (i = count - 1; i >= 0; i--)
  729. generic_phy_power_off(&usb_phys[i]);
  730. for (i = 0; i < count; i++)
  731. generic_phy_exit(&usb_phys[i]);
  732. return ret;
  733. phys_init_err:
  734. for (; i >= 0; i--)
  735. generic_phy_exit(&usb_phys[i]);
  736. return ret;
  737. }
  738. int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
  739. {
  740. int i, ret;
  741. for (i = 0; i < num_phys; i++) {
  742. if (!generic_phy_valid(&usb_phys[i]))
  743. continue;
  744. ret = generic_phy_power_off(&usb_phys[i]);
  745. ret |= generic_phy_exit(&usb_phys[i]);
  746. if (ret) {
  747. pr_err("Can't shutdown USB PHY%d for %s\n",
  748. i, dev->name);
  749. }
  750. }
  751. return 0;
  752. }
  753. #endif
  754. #if CONFIG_IS_ENABLED(DM_USB)
  755. void dwc3_of_parse(struct dwc3 *dwc)
  756. {
  757. const u8 *tmp;
  758. struct udevice *dev = dwc->dev;
  759. u8 lpm_nyet_threshold;
  760. u8 tx_de_emphasis;
  761. u8 hird_threshold;
  762. /* default to highest possible threshold */
  763. lpm_nyet_threshold = 0xff;
  764. /* default to -3.5dB de-emphasis */
  765. tx_de_emphasis = 1;
  766. /*
  767. * default to assert utmi_sleep_n and use maximum allowed HIRD
  768. * threshold value of 0b1100
  769. */
  770. hird_threshold = 12;
  771. dwc->has_lpm_erratum = dev_read_bool(dev,
  772. "snps,has-lpm-erratum");
  773. tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
  774. if (tmp)
  775. lpm_nyet_threshold = *tmp;
  776. dwc->is_utmi_l1_suspend = dev_read_bool(dev,
  777. "snps,is-utmi-l1-suspend");
  778. tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
  779. if (tmp)
  780. hird_threshold = *tmp;
  781. dwc->disable_scramble_quirk = dev_read_bool(dev,
  782. "snps,disable_scramble_quirk");
  783. dwc->u2exit_lfps_quirk = dev_read_bool(dev,
  784. "snps,u2exit_lfps_quirk");
  785. dwc->u2ss_inp3_quirk = dev_read_bool(dev,
  786. "snps,u2ss_inp3_quirk");
  787. dwc->req_p1p2p3_quirk = dev_read_bool(dev,
  788. "snps,req_p1p2p3_quirk");
  789. dwc->del_p1p2p3_quirk = dev_read_bool(dev,
  790. "snps,del_p1p2p3_quirk");
  791. dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
  792. "snps,del_phy_power_chg_quirk");
  793. dwc->lfps_filter_quirk = dev_read_bool(dev,
  794. "snps,lfps_filter_quirk");
  795. dwc->rx_detect_poll_quirk = dev_read_bool(dev,
  796. "snps,rx_detect_poll_quirk");
  797. dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
  798. "snps,dis_u3_susphy_quirk");
  799. dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
  800. "snps,dis_u2_susphy_quirk");
  801. dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
  802. "snps,tx_de_emphasis_quirk");
  803. tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
  804. if (tmp)
  805. tx_de_emphasis = *tmp;
  806. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  807. dwc->tx_de_emphasis = tx_de_emphasis;
  808. dwc->hird_threshold = hird_threshold
  809. | (dwc->is_utmi_l1_suspend << 4);
  810. }
  811. int dwc3_init(struct dwc3 *dwc)
  812. {
  813. int ret;
  814. dwc3_cache_hwparams(dwc);
  815. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  816. if (ret) {
  817. dev_err(dwc->dev, "failed to allocate event buffers\n");
  818. return -ENOMEM;
  819. }
  820. ret = dwc3_core_init(dwc);
  821. if (ret) {
  822. dev_err(dev, "failed to initialize core\n");
  823. goto core_fail;
  824. }
  825. ret = dwc3_event_buffers_setup(dwc);
  826. if (ret) {
  827. dev_err(dwc->dev, "failed to setup event buffers\n");
  828. goto event_fail;
  829. }
  830. ret = dwc3_core_init_mode(dwc);
  831. if (ret)
  832. goto mode_fail;
  833. return 0;
  834. mode_fail:
  835. dwc3_event_buffers_cleanup(dwc);
  836. event_fail:
  837. dwc3_core_exit(dwc);
  838. core_fail:
  839. dwc3_free_event_buffers(dwc);
  840. return ret;
  841. }
  842. void dwc3_remove(struct dwc3 *dwc)
  843. {
  844. dwc3_core_exit_mode(dwc);
  845. dwc3_event_buffers_cleanup(dwc);
  846. dwc3_free_event_buffers(dwc);
  847. dwc3_core_exit(dwc);
  848. kfree(dwc->mem);
  849. }
  850. #endif