ufs.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * ufs.c - Universal Flash Subsystem (UFS) driver
  4. *
  5. * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
  6. * to u-boot.
  7. *
  8. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
  9. */
  10. #include <charset.h>
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/devres.h>
  15. #include <dm/lists.h>
  16. #include <dm/device-internal.h>
  17. #include <malloc.h>
  18. #include <hexdump.h>
  19. #include <scsi.h>
  20. #include <linux/dma-mapping.h>
  21. #include "ufs.h"
  22. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  23. UTP_TASK_REQ_COMPL |\
  24. UFSHCD_ERROR_MASK)
  25. /* maximum number of link-startup retries */
  26. #define DME_LINKSTARTUP_RETRIES 3
  27. /* maximum number of retries for a general UIC command */
  28. #define UFS_UIC_COMMAND_RETRIES 3
  29. /* Query request retries */
  30. #define QUERY_REQ_RETRIES 3
  31. /* Query request timeout */
  32. #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  33. /* maximum timeout in ms for a general UIC command */
  34. #define UFS_UIC_CMD_TIMEOUT 1000
  35. /* NOP OUT retries waiting for NOP IN response */
  36. #define NOP_OUT_RETRIES 10
  37. /* Timeout after 30 msecs if NOP OUT hangs without response */
  38. #define NOP_OUT_TIMEOUT 30 /* msecs */
  39. /* Only use one Task Tag for all requests */
  40. #define TASK_TAG 0
  41. /* Expose the flag value from utp_upiu_query.value */
  42. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  43. #define MAX_PRDT_ENTRY 262144
  44. /* maximum bytes per request */
  45. #define UFS_MAX_BYTES (128 * 256 * 1024)
  46. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
  47. static inline void ufshcd_hba_stop(struct ufs_hba *hba);
  48. static int ufshcd_hba_enable(struct ufs_hba *hba);
  49. /*
  50. * ufshcd_wait_for_register - wait for register value to change
  51. */
  52. static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  53. u32 val, unsigned long timeout_ms)
  54. {
  55. int err = 0;
  56. unsigned long start = get_timer(0);
  57. /* ignore bits that we don't intend to wait on */
  58. val = val & mask;
  59. while ((ufshcd_readl(hba, reg) & mask) != val) {
  60. if (get_timer(start) > timeout_ms) {
  61. if ((ufshcd_readl(hba, reg) & mask) != val)
  62. err = -ETIMEDOUT;
  63. break;
  64. }
  65. }
  66. return err;
  67. }
  68. /**
  69. * ufshcd_init_pwr_info - setting the POR (power on reset)
  70. * values in hba power info
  71. */
  72. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  73. {
  74. hba->pwr_info.gear_rx = UFS_PWM_G1;
  75. hba->pwr_info.gear_tx = UFS_PWM_G1;
  76. hba->pwr_info.lane_rx = 1;
  77. hba->pwr_info.lane_tx = 1;
  78. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  79. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  80. hba->pwr_info.hs_rate = 0;
  81. }
  82. /**
  83. * ufshcd_print_pwr_info - print power params as saved in hba
  84. * power info
  85. */
  86. static void ufshcd_print_pwr_info(struct ufs_hba *hba)
  87. {
  88. static const char * const names[] = {
  89. "INVALID MODE",
  90. "FAST MODE",
  91. "SLOW_MODE",
  92. "INVALID MODE",
  93. "FASTAUTO_MODE",
  94. "SLOWAUTO_MODE",
  95. "INVALID MODE",
  96. };
  97. dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
  98. hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
  99. hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
  100. names[hba->pwr_info.pwr_rx],
  101. names[hba->pwr_info.pwr_tx],
  102. hba->pwr_info.hs_rate);
  103. }
  104. /**
  105. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  106. * to accept UIC commands
  107. */
  108. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  109. {
  110. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  111. return true;
  112. else
  113. return false;
  114. }
  115. /**
  116. * ufshcd_get_uic_cmd_result - Get the UIC command result
  117. */
  118. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  119. {
  120. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  121. MASK_UIC_COMMAND_RESULT;
  122. }
  123. /**
  124. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  125. */
  126. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  127. {
  128. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  129. }
  130. /**
  131. * ufshcd_is_device_present - Check if any device connected to
  132. * the host controller
  133. */
  134. static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
  135. {
  136. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  137. DEVICE_PRESENT) ? true : false;
  138. }
  139. /**
  140. * ufshcd_send_uic_cmd - UFS Interconnect layer command API
  141. *
  142. */
  143. static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  144. {
  145. unsigned long start = 0;
  146. u32 intr_status;
  147. u32 enabled_intr_status;
  148. if (!ufshcd_ready_for_uic_cmd(hba)) {
  149. dev_err(hba->dev,
  150. "Controller not ready to accept UIC commands\n");
  151. return -EIO;
  152. }
  153. debug("sending uic command:%d\n", uic_cmd->command);
  154. /* Write Args */
  155. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  156. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  157. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  158. /* Write UIC Cmd */
  159. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  160. REG_UIC_COMMAND);
  161. start = get_timer(0);
  162. do {
  163. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  164. enabled_intr_status = intr_status & hba->intr_mask;
  165. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  166. if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
  167. dev_err(hba->dev,
  168. "Timedout waiting for UIC response\n");
  169. return -ETIMEDOUT;
  170. }
  171. if (enabled_intr_status & UFSHCD_ERROR_MASK) {
  172. dev_err(hba->dev, "Error in status:%08x\n",
  173. enabled_intr_status);
  174. return -1;
  175. }
  176. } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
  177. uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
  178. uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
  179. debug("Sent successfully\n");
  180. return 0;
  181. }
  182. /**
  183. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  184. *
  185. */
  186. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
  187. u32 mib_val, u8 peer)
  188. {
  189. struct uic_command uic_cmd = {0};
  190. static const char *const action[] = {
  191. "dme-set",
  192. "dme-peer-set"
  193. };
  194. const char *set = action[!!peer];
  195. int ret;
  196. int retries = UFS_UIC_COMMAND_RETRIES;
  197. uic_cmd.command = peer ?
  198. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  199. uic_cmd.argument1 = attr_sel;
  200. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  201. uic_cmd.argument3 = mib_val;
  202. do {
  203. /* for peer attributes we retry upon failure */
  204. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  205. if (ret)
  206. dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  207. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  208. } while (ret && peer && --retries);
  209. if (ret)
  210. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
  211. set, UIC_GET_ATTR_ID(attr_sel), mib_val,
  212. UFS_UIC_COMMAND_RETRIES - retries);
  213. return ret;
  214. }
  215. /**
  216. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  217. *
  218. */
  219. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  220. u32 *mib_val, u8 peer)
  221. {
  222. struct uic_command uic_cmd = {0};
  223. static const char *const action[] = {
  224. "dme-get",
  225. "dme-peer-get"
  226. };
  227. const char *get = action[!!peer];
  228. int ret;
  229. int retries = UFS_UIC_COMMAND_RETRIES;
  230. uic_cmd.command = peer ?
  231. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  232. uic_cmd.argument1 = attr_sel;
  233. do {
  234. /* for peer attributes we retry upon failure */
  235. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  236. if (ret)
  237. dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
  238. get, UIC_GET_ATTR_ID(attr_sel), ret);
  239. } while (ret && peer && --retries);
  240. if (ret)
  241. dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
  242. get, UIC_GET_ATTR_ID(attr_sel),
  243. UFS_UIC_COMMAND_RETRIES - retries);
  244. if (mib_val && !ret)
  245. *mib_val = uic_cmd.argument3;
  246. return ret;
  247. }
  248. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  249. {
  250. u32 tx_lanes, i, err = 0;
  251. if (!peer)
  252. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  253. &tx_lanes);
  254. else
  255. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  256. &tx_lanes);
  257. for (i = 0; i < tx_lanes; i++) {
  258. if (!peer)
  259. err = ufshcd_dme_set(hba,
  260. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  261. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  262. 0);
  263. else
  264. err = ufshcd_dme_peer_set(hba,
  265. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  266. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  267. 0);
  268. if (err) {
  269. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  270. __func__, peer, i, err);
  271. break;
  272. }
  273. }
  274. return err;
  275. }
  276. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  277. {
  278. return ufshcd_disable_tx_lcc(hba, true);
  279. }
  280. /**
  281. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  282. *
  283. */
  284. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  285. {
  286. struct uic_command uic_cmd = {0};
  287. int ret;
  288. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  289. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  290. if (ret)
  291. dev_dbg(hba->dev,
  292. "dme-link-startup: error code %d\n", ret);
  293. return ret;
  294. }
  295. /**
  296. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  297. *
  298. */
  299. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  300. {
  301. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  302. }
  303. /**
  304. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  305. */
  306. static inline int ufshcd_get_lists_status(u32 reg)
  307. {
  308. return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
  309. }
  310. /**
  311. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  312. * When run-stop registers are set to 1, it indicates the
  313. * host controller that it can process the requests
  314. */
  315. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  316. {
  317. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  318. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  319. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  320. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  321. }
  322. /**
  323. * ufshcd_enable_intr - enable interrupts
  324. */
  325. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  326. {
  327. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  328. u32 rw;
  329. if (hba->version == UFSHCI_VERSION_10) {
  330. rw = set & INTERRUPT_MASK_RW_VER_10;
  331. set = rw | ((set ^ intrs) & intrs);
  332. } else {
  333. set |= intrs;
  334. }
  335. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  336. hba->intr_mask = set;
  337. }
  338. /**
  339. * ufshcd_make_hba_operational - Make UFS controller operational
  340. *
  341. * To bring UFS host controller to operational state,
  342. * 1. Enable required interrupts
  343. * 2. Configure interrupt aggregation
  344. * 3. Program UTRL and UTMRL base address
  345. * 4. Configure run-stop-registers
  346. *
  347. */
  348. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  349. {
  350. int err = 0;
  351. u32 reg;
  352. /* Enable required interrupts */
  353. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  354. /* Disable interrupt aggregation */
  355. ufshcd_disable_intr_aggr(hba);
  356. /* Configure UTRL and UTMRL base address registers */
  357. ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
  358. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  359. ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
  360. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  361. ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
  362. REG_UTP_TASK_REQ_LIST_BASE_L);
  363. ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
  364. REG_UTP_TASK_REQ_LIST_BASE_H);
  365. /*
  366. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  367. */
  368. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  369. if (!(ufshcd_get_lists_status(reg))) {
  370. ufshcd_enable_run_stop_reg(hba);
  371. } else {
  372. dev_err(hba->dev,
  373. "Host controller not ready to process requests");
  374. err = -EIO;
  375. goto out;
  376. }
  377. out:
  378. return err;
  379. }
  380. /**
  381. * ufshcd_link_startup - Initialize unipro link startup
  382. */
  383. static int ufshcd_link_startup(struct ufs_hba *hba)
  384. {
  385. int ret;
  386. int retries = DME_LINKSTARTUP_RETRIES;
  387. bool link_startup_again = true;
  388. link_startup:
  389. do {
  390. ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
  391. ret = ufshcd_dme_link_startup(hba);
  392. /* check if device is detected by inter-connect layer */
  393. if (!ret && !ufshcd_is_device_present(hba)) {
  394. dev_err(hba->dev, "%s: Device not present\n", __func__);
  395. ret = -ENXIO;
  396. goto out;
  397. }
  398. /*
  399. * DME link lost indication is only received when link is up,
  400. * but we can't be sure if the link is up until link startup
  401. * succeeds. So reset the local Uni-Pro and try again.
  402. */
  403. if (ret && ufshcd_hba_enable(hba))
  404. goto out;
  405. } while (ret && retries--);
  406. if (ret)
  407. /* failed to get the link up... retire */
  408. goto out;
  409. if (link_startup_again) {
  410. link_startup_again = false;
  411. retries = DME_LINKSTARTUP_RETRIES;
  412. goto link_startup;
  413. }
  414. /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
  415. ufshcd_init_pwr_info(hba);
  416. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  417. ret = ufshcd_disable_device_tx_lcc(hba);
  418. if (ret)
  419. goto out;
  420. }
  421. /* Include any host controller configuration via UIC commands */
  422. ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
  423. if (ret)
  424. goto out;
  425. ret = ufshcd_make_hba_operational(hba);
  426. out:
  427. if (ret)
  428. dev_err(hba->dev, "link startup failed %d\n", ret);
  429. return ret;
  430. }
  431. /**
  432. * ufshcd_hba_stop - Send controller to reset state
  433. */
  434. static inline void ufshcd_hba_stop(struct ufs_hba *hba)
  435. {
  436. int err;
  437. ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
  438. err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
  439. CONTROLLER_ENABLE, CONTROLLER_DISABLE,
  440. 10);
  441. if (err)
  442. dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
  443. }
  444. /**
  445. * ufshcd_is_hba_active - Get controller state
  446. */
  447. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
  448. {
  449. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
  450. ? false : true;
  451. }
  452. /**
  453. * ufshcd_hba_start - Start controller initialization sequence
  454. */
  455. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  456. {
  457. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  458. }
  459. /**
  460. * ufshcd_hba_enable - initialize the controller
  461. */
  462. static int ufshcd_hba_enable(struct ufs_hba *hba)
  463. {
  464. int retry;
  465. if (!ufshcd_is_hba_active(hba))
  466. /* change controller state to "reset state" */
  467. ufshcd_hba_stop(hba);
  468. ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
  469. /* start controller initialization sequence */
  470. ufshcd_hba_start(hba);
  471. /*
  472. * To initialize a UFS host controller HCE bit must be set to 1.
  473. * During initialization the HCE bit value changes from 1->0->1.
  474. * When the host controller completes initialization sequence
  475. * it sets the value of HCE bit to 1. The same HCE bit is read back
  476. * to check if the controller has completed initialization sequence.
  477. * So without this delay the value HCE = 1, set in the previous
  478. * instruction might be read back.
  479. * This delay can be changed based on the controller.
  480. */
  481. mdelay(1);
  482. /* wait for the host controller to complete initialization */
  483. retry = 10;
  484. while (ufshcd_is_hba_active(hba)) {
  485. if (retry) {
  486. retry--;
  487. } else {
  488. dev_err(hba->dev, "Controller enable failed\n");
  489. return -EIO;
  490. }
  491. mdelay(5);
  492. }
  493. /* enable UIC related interrupts */
  494. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  495. ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
  496. return 0;
  497. }
  498. /**
  499. * ufshcd_host_memory_configure - configure local reference block with
  500. * memory offsets
  501. */
  502. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  503. {
  504. struct utp_transfer_req_desc *utrdlp;
  505. dma_addr_t cmd_desc_dma_addr;
  506. u16 response_offset;
  507. u16 prdt_offset;
  508. utrdlp = hba->utrdl;
  509. cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
  510. utrdlp->command_desc_base_addr_lo =
  511. cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
  512. utrdlp->command_desc_base_addr_hi =
  513. cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
  514. response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
  515. prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
  516. utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
  517. utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
  518. utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  519. hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
  520. hba->ucd_rsp_ptr =
  521. (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
  522. hba->ucd_prdt_ptr =
  523. (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
  524. }
  525. /**
  526. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  527. */
  528. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  529. {
  530. /* Allocate one Transfer Request Descriptor
  531. * Should be aligned to 1k boundary.
  532. */
  533. hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
  534. if (!hba->utrdl) {
  535. dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
  536. return -ENOMEM;
  537. }
  538. /* Allocate one Command Descriptor
  539. * Should be aligned to 1k boundary.
  540. */
  541. hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
  542. if (!hba->ucdl) {
  543. dev_err(hba->dev, "Command descriptor memory allocation failed\n");
  544. return -ENOMEM;
  545. }
  546. return 0;
  547. }
  548. /**
  549. * ufshcd_get_intr_mask - Get the interrupt bit mask
  550. */
  551. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  552. {
  553. u32 intr_mask = 0;
  554. switch (hba->version) {
  555. case UFSHCI_VERSION_10:
  556. intr_mask = INTERRUPT_MASK_ALL_VER_10;
  557. break;
  558. case UFSHCI_VERSION_11:
  559. case UFSHCI_VERSION_20:
  560. intr_mask = INTERRUPT_MASK_ALL_VER_11;
  561. break;
  562. case UFSHCI_VERSION_21:
  563. default:
  564. intr_mask = INTERRUPT_MASK_ALL_VER_21;
  565. break;
  566. }
  567. return intr_mask;
  568. }
  569. /**
  570. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  571. */
  572. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  573. {
  574. return ufshcd_readl(hba, REG_UFS_VERSION);
  575. }
  576. /**
  577. * ufshcd_get_upmcrs - Get the power mode change request status
  578. */
  579. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  580. {
  581. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  582. }
  583. /**
  584. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  585. * descriptor according to request
  586. */
  587. static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
  588. u32 *upiu_flags,
  589. enum dma_data_direction cmd_dir)
  590. {
  591. u32 data_direction;
  592. u32 dword_0;
  593. if (cmd_dir == DMA_FROM_DEVICE) {
  594. data_direction = UTP_DEVICE_TO_HOST;
  595. *upiu_flags = UPIU_CMD_FLAGS_READ;
  596. } else if (cmd_dir == DMA_TO_DEVICE) {
  597. data_direction = UTP_HOST_TO_DEVICE;
  598. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  599. } else {
  600. data_direction = UTP_NO_DATA_TRANSFER;
  601. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  602. }
  603. dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
  604. /* Enable Interrupt for command */
  605. dword_0 |= UTP_REQ_DESC_INT_CMD;
  606. /* Transfer request descriptor header fields */
  607. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  608. /* dword_1 is reserved, hence it is set to 0 */
  609. req_desc->header.dword_1 = 0;
  610. /*
  611. * assigning invalid value for command status. Controller
  612. * updates OCS on command completion, with the command
  613. * status
  614. */
  615. req_desc->header.dword_2 =
  616. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  617. /* dword_3 is reserved, hence it is set to 0 */
  618. req_desc->header.dword_3 = 0;
  619. req_desc->prd_table_length = 0;
  620. }
  621. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  622. u32 upiu_flags)
  623. {
  624. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  625. struct ufs_query *query = &hba->dev_cmd.query;
  626. u16 len = be16_to_cpu(query->request.upiu_req.length);
  627. /* Query request header */
  628. ucd_req_ptr->header.dword_0 =
  629. UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
  630. upiu_flags, 0, TASK_TAG);
  631. ucd_req_ptr->header.dword_1 =
  632. UPIU_HEADER_DWORD(0, query->request.query_func,
  633. 0, 0);
  634. /* Data segment length only need for WRITE_DESC */
  635. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  636. ucd_req_ptr->header.dword_2 =
  637. UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
  638. else
  639. ucd_req_ptr->header.dword_2 = 0;
  640. /* Copy the Query Request buffer as is */
  641. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
  642. /* Copy the Descriptor */
  643. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  644. memcpy(ucd_req_ptr + 1, query->descriptor, len);
  645. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  646. }
  647. static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
  648. {
  649. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  650. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  651. /* command descriptor fields */
  652. ucd_req_ptr->header.dword_0 =
  653. UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, 0x1f);
  654. /* clear rest of the fields of basic header */
  655. ucd_req_ptr->header.dword_1 = 0;
  656. ucd_req_ptr->header.dword_2 = 0;
  657. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  658. }
  659. /**
  660. * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
  661. * for Device Management Purposes
  662. */
  663. static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
  664. enum dev_cmd_type cmd_type)
  665. {
  666. u32 upiu_flags;
  667. int ret = 0;
  668. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  669. hba->dev_cmd.type = cmd_type;
  670. ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
  671. switch (cmd_type) {
  672. case DEV_CMD_TYPE_QUERY:
  673. ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
  674. break;
  675. case DEV_CMD_TYPE_NOP:
  676. ufshcd_prepare_utp_nop_upiu(hba);
  677. break;
  678. default:
  679. ret = -EINVAL;
  680. }
  681. return ret;
  682. }
  683. static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  684. {
  685. unsigned long start;
  686. u32 intr_status;
  687. u32 enabled_intr_status;
  688. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  689. start = get_timer(0);
  690. do {
  691. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  692. enabled_intr_status = intr_status & hba->intr_mask;
  693. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  694. if (get_timer(start) > QUERY_REQ_TIMEOUT) {
  695. dev_err(hba->dev,
  696. "Timedout waiting for UTP response\n");
  697. return -ETIMEDOUT;
  698. }
  699. if (enabled_intr_status & UFSHCD_ERROR_MASK) {
  700. dev_err(hba->dev, "Error in status:%08x\n",
  701. enabled_intr_status);
  702. return -1;
  703. }
  704. } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
  705. return 0;
  706. }
  707. /**
  708. * ufshcd_get_req_rsp - returns the TR response transaction type
  709. */
  710. static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  711. {
  712. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  713. }
  714. /**
  715. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  716. *
  717. */
  718. static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
  719. {
  720. return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
  721. }
  722. static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  723. {
  724. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  725. }
  726. static int ufshcd_check_query_response(struct ufs_hba *hba)
  727. {
  728. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  729. /* Get the UPIU response */
  730. query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
  731. UPIU_RSP_CODE_OFFSET;
  732. return query_res->response;
  733. }
  734. /**
  735. * ufshcd_copy_query_response() - Copy the Query Response and the data
  736. * descriptor
  737. */
  738. static int ufshcd_copy_query_response(struct ufs_hba *hba)
  739. {
  740. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  741. memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  742. /* Get the descriptor */
  743. if (hba->dev_cmd.query.descriptor &&
  744. hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  745. u8 *descp = (u8 *)hba->ucd_rsp_ptr +
  746. GENERAL_UPIU_REQUEST_SIZE;
  747. u16 resp_len;
  748. u16 buf_len;
  749. /* data segment length */
  750. resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
  751. MASK_QUERY_DATA_SEG_LEN;
  752. buf_len =
  753. be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
  754. if (likely(buf_len >= resp_len)) {
  755. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  756. } else {
  757. dev_warn(hba->dev,
  758. "%s: Response size is bigger than buffer",
  759. __func__);
  760. return -EINVAL;
  761. }
  762. }
  763. return 0;
  764. }
  765. /**
  766. * ufshcd_exec_dev_cmd - API for sending device management requests
  767. */
  768. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
  769. int timeout)
  770. {
  771. int err;
  772. int resp;
  773. err = ufshcd_comp_devman_upiu(hba, cmd_type);
  774. if (err)
  775. return err;
  776. err = ufshcd_send_command(hba, TASK_TAG);
  777. if (err)
  778. return err;
  779. err = ufshcd_get_tr_ocs(hba);
  780. if (err) {
  781. dev_err(hba->dev, "Error in OCS:%d\n", err);
  782. return -EINVAL;
  783. }
  784. resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
  785. switch (resp) {
  786. case UPIU_TRANSACTION_NOP_IN:
  787. break;
  788. case UPIU_TRANSACTION_QUERY_RSP:
  789. err = ufshcd_check_query_response(hba);
  790. if (!err)
  791. err = ufshcd_copy_query_response(hba);
  792. break;
  793. case UPIU_TRANSACTION_REJECT_UPIU:
  794. /* TODO: handle Reject UPIU Response */
  795. err = -EPERM;
  796. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  797. __func__);
  798. break;
  799. default:
  800. err = -EINVAL;
  801. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  802. __func__, resp);
  803. }
  804. return err;
  805. }
  806. /**
  807. * ufshcd_init_query() - init the query response and request parameters
  808. */
  809. static inline void ufshcd_init_query(struct ufs_hba *hba,
  810. struct ufs_query_req **request,
  811. struct ufs_query_res **response,
  812. enum query_opcode opcode,
  813. u8 idn, u8 index, u8 selector)
  814. {
  815. *request = &hba->dev_cmd.query.request;
  816. *response = &hba->dev_cmd.query.response;
  817. memset(*request, 0, sizeof(struct ufs_query_req));
  818. memset(*response, 0, sizeof(struct ufs_query_res));
  819. (*request)->upiu_req.opcode = opcode;
  820. (*request)->upiu_req.idn = idn;
  821. (*request)->upiu_req.index = index;
  822. (*request)->upiu_req.selector = selector;
  823. }
  824. /**
  825. * ufshcd_query_flag() - API function for sending flag query requests
  826. */
  827. int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  828. enum flag_idn idn, bool *flag_res)
  829. {
  830. struct ufs_query_req *request = NULL;
  831. struct ufs_query_res *response = NULL;
  832. int err, index = 0, selector = 0;
  833. int timeout = QUERY_REQ_TIMEOUT;
  834. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  835. selector);
  836. switch (opcode) {
  837. case UPIU_QUERY_OPCODE_SET_FLAG:
  838. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  839. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  840. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  841. break;
  842. case UPIU_QUERY_OPCODE_READ_FLAG:
  843. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  844. if (!flag_res) {
  845. /* No dummy reads */
  846. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  847. __func__);
  848. err = -EINVAL;
  849. goto out;
  850. }
  851. break;
  852. default:
  853. dev_err(hba->dev,
  854. "%s: Expected query flag opcode but got = %d\n",
  855. __func__, opcode);
  856. err = -EINVAL;
  857. goto out;
  858. }
  859. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
  860. if (err) {
  861. dev_err(hba->dev,
  862. "%s: Sending flag query for idn %d failed, err = %d\n",
  863. __func__, idn, err);
  864. goto out;
  865. }
  866. if (flag_res)
  867. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  868. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  869. out:
  870. return err;
  871. }
  872. static int ufshcd_query_flag_retry(struct ufs_hba *hba,
  873. enum query_opcode opcode,
  874. enum flag_idn idn, bool *flag_res)
  875. {
  876. int ret;
  877. int retries;
  878. for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
  879. ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
  880. if (ret)
  881. dev_dbg(hba->dev,
  882. "%s: failed with error %d, retries %d\n",
  883. __func__, ret, retries);
  884. else
  885. break;
  886. }
  887. if (ret)
  888. dev_err(hba->dev,
  889. "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
  890. __func__, opcode, idn, ret, retries);
  891. return ret;
  892. }
  893. static int __ufshcd_query_descriptor(struct ufs_hba *hba,
  894. enum query_opcode opcode,
  895. enum desc_idn idn, u8 index, u8 selector,
  896. u8 *desc_buf, int *buf_len)
  897. {
  898. struct ufs_query_req *request = NULL;
  899. struct ufs_query_res *response = NULL;
  900. int err;
  901. if (!desc_buf) {
  902. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  903. __func__, opcode);
  904. err = -EINVAL;
  905. goto out;
  906. }
  907. if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  908. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  909. __func__, *buf_len);
  910. err = -EINVAL;
  911. goto out;
  912. }
  913. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  914. selector);
  915. hba->dev_cmd.query.descriptor = desc_buf;
  916. request->upiu_req.length = cpu_to_be16(*buf_len);
  917. switch (opcode) {
  918. case UPIU_QUERY_OPCODE_WRITE_DESC:
  919. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  920. break;
  921. case UPIU_QUERY_OPCODE_READ_DESC:
  922. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  923. break;
  924. default:
  925. dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  926. __func__, opcode);
  927. err = -EINVAL;
  928. goto out;
  929. }
  930. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  931. if (err) {
  932. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  933. __func__, opcode, idn, index, err);
  934. goto out;
  935. }
  936. hba->dev_cmd.query.descriptor = NULL;
  937. *buf_len = be16_to_cpu(response->upiu_res.length);
  938. out:
  939. return err;
  940. }
  941. /**
  942. * ufshcd_query_descriptor_retry - API function for sending descriptor requests
  943. */
  944. int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
  945. enum desc_idn idn, u8 index, u8 selector,
  946. u8 *desc_buf, int *buf_len)
  947. {
  948. int err;
  949. int retries;
  950. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  951. err = __ufshcd_query_descriptor(hba, opcode, idn, index,
  952. selector, desc_buf, buf_len);
  953. if (!err || err == -EINVAL)
  954. break;
  955. }
  956. return err;
  957. }
  958. /**
  959. * ufshcd_read_desc_length - read the specified descriptor length from header
  960. */
  961. static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
  962. int desc_index, int *desc_length)
  963. {
  964. int ret;
  965. u8 header[QUERY_DESC_HDR_SIZE];
  966. int header_len = QUERY_DESC_HDR_SIZE;
  967. if (desc_id >= QUERY_DESC_IDN_MAX)
  968. return -EINVAL;
  969. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  970. desc_id, desc_index, 0, header,
  971. &header_len);
  972. if (ret) {
  973. dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
  974. __func__, desc_id);
  975. return ret;
  976. } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
  977. dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
  978. __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
  979. desc_id);
  980. ret = -EINVAL;
  981. }
  982. *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
  983. return ret;
  984. }
  985. static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
  986. {
  987. int err;
  988. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
  989. &hba->desc_size.dev_desc);
  990. if (err)
  991. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  992. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
  993. &hba->desc_size.pwr_desc);
  994. if (err)
  995. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  996. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
  997. &hba->desc_size.interc_desc);
  998. if (err)
  999. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  1000. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
  1001. &hba->desc_size.conf_desc);
  1002. if (err)
  1003. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  1004. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
  1005. &hba->desc_size.unit_desc);
  1006. if (err)
  1007. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  1008. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
  1009. &hba->desc_size.geom_desc);
  1010. if (err)
  1011. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  1012. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
  1013. &hba->desc_size.hlth_desc);
  1014. if (err)
  1015. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  1016. }
  1017. /**
  1018. * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
  1019. *
  1020. */
  1021. int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
  1022. int *desc_len)
  1023. {
  1024. switch (desc_id) {
  1025. case QUERY_DESC_IDN_DEVICE:
  1026. *desc_len = hba->desc_size.dev_desc;
  1027. break;
  1028. case QUERY_DESC_IDN_POWER:
  1029. *desc_len = hba->desc_size.pwr_desc;
  1030. break;
  1031. case QUERY_DESC_IDN_GEOMETRY:
  1032. *desc_len = hba->desc_size.geom_desc;
  1033. break;
  1034. case QUERY_DESC_IDN_CONFIGURATION:
  1035. *desc_len = hba->desc_size.conf_desc;
  1036. break;
  1037. case QUERY_DESC_IDN_UNIT:
  1038. *desc_len = hba->desc_size.unit_desc;
  1039. break;
  1040. case QUERY_DESC_IDN_INTERCONNECT:
  1041. *desc_len = hba->desc_size.interc_desc;
  1042. break;
  1043. case QUERY_DESC_IDN_STRING:
  1044. *desc_len = QUERY_DESC_MAX_SIZE;
  1045. break;
  1046. case QUERY_DESC_IDN_HEALTH:
  1047. *desc_len = hba->desc_size.hlth_desc;
  1048. break;
  1049. case QUERY_DESC_IDN_RFU_0:
  1050. case QUERY_DESC_IDN_RFU_1:
  1051. *desc_len = 0;
  1052. break;
  1053. default:
  1054. *desc_len = 0;
  1055. return -EINVAL;
  1056. }
  1057. return 0;
  1058. }
  1059. EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
  1060. /**
  1061. * ufshcd_read_desc_param - read the specified descriptor parameter
  1062. *
  1063. */
  1064. int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
  1065. int desc_index, u8 param_offset, u8 *param_read_buf,
  1066. u8 param_size)
  1067. {
  1068. int ret;
  1069. u8 *desc_buf;
  1070. int buff_len;
  1071. bool is_kmalloc = true;
  1072. /* Safety check */
  1073. if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
  1074. return -EINVAL;
  1075. /* Get the max length of descriptor from structure filled up at probe
  1076. * time.
  1077. */
  1078. ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
  1079. /* Sanity checks */
  1080. if (ret || !buff_len) {
  1081. dev_err(hba->dev, "%s: Failed to get full descriptor length",
  1082. __func__);
  1083. return ret;
  1084. }
  1085. /* Check whether we need temp memory */
  1086. if (param_offset != 0 || param_size < buff_len) {
  1087. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1088. if (!desc_buf)
  1089. return -ENOMEM;
  1090. } else {
  1091. desc_buf = param_read_buf;
  1092. is_kmalloc = false;
  1093. }
  1094. /* Request for full descriptor */
  1095. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  1096. desc_id, desc_index, 0, desc_buf,
  1097. &buff_len);
  1098. if (ret) {
  1099. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
  1100. __func__, desc_id, desc_index, param_offset, ret);
  1101. goto out;
  1102. }
  1103. /* Sanity check */
  1104. if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
  1105. dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
  1106. __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
  1107. ret = -EINVAL;
  1108. goto out;
  1109. }
  1110. /* Check wherher we will not copy more data, than available */
  1111. if (is_kmalloc && param_size > buff_len)
  1112. param_size = buff_len;
  1113. if (is_kmalloc)
  1114. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  1115. out:
  1116. if (is_kmalloc)
  1117. kfree(desc_buf);
  1118. return ret;
  1119. }
  1120. /* replace non-printable or non-ASCII characters with spaces */
  1121. static inline void ufshcd_remove_non_printable(uint8_t *val)
  1122. {
  1123. if (!val)
  1124. return;
  1125. if (*val < 0x20 || *val > 0x7e)
  1126. *val = ' ';
  1127. }
  1128. /**
  1129. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  1130. * state) and waits for it to take effect.
  1131. *
  1132. */
  1133. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  1134. {
  1135. unsigned long start = 0;
  1136. u8 status;
  1137. int ret;
  1138. ret = ufshcd_send_uic_cmd(hba, cmd);
  1139. if (ret) {
  1140. dev_err(hba->dev,
  1141. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1142. cmd->command, cmd->argument3, ret);
  1143. return ret;
  1144. }
  1145. start = get_timer(0);
  1146. do {
  1147. status = ufshcd_get_upmcrs(hba);
  1148. if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
  1149. dev_err(hba->dev,
  1150. "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
  1151. cmd->command, status);
  1152. ret = (status != PWR_OK) ? status : -1;
  1153. break;
  1154. }
  1155. } while (status != PWR_LOCAL);
  1156. return ret;
  1157. }
  1158. /**
  1159. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
  1160. * using DME_SET primitives.
  1161. */
  1162. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  1163. {
  1164. struct uic_command uic_cmd = {0};
  1165. int ret;
  1166. uic_cmd.command = UIC_CMD_DME_SET;
  1167. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  1168. uic_cmd.argument3 = mode;
  1169. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  1170. return ret;
  1171. }
  1172. static
  1173. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
  1174. struct scsi_cmd *pccb, u32 upiu_flags)
  1175. {
  1176. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  1177. unsigned int cdb_len;
  1178. /* command descriptor fields */
  1179. ucd_req_ptr->header.dword_0 =
  1180. UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
  1181. pccb->lun, TASK_TAG);
  1182. ucd_req_ptr->header.dword_1 =
  1183. UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1184. /* Total EHS length and Data segment length will be zero */
  1185. ucd_req_ptr->header.dword_2 = 0;
  1186. ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
  1187. cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
  1188. memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
  1189. memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
  1190. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1191. }
  1192. static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
  1193. unsigned char *buf, ulong len)
  1194. {
  1195. entry->size = cpu_to_le32(len) | GENMASK(1, 0);
  1196. entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
  1197. entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
  1198. }
  1199. static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
  1200. {
  1201. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  1202. struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
  1203. ulong datalen = pccb->datalen;
  1204. int table_length;
  1205. u8 *buf;
  1206. int i;
  1207. if (!datalen) {
  1208. req_desc->prd_table_length = 0;
  1209. return;
  1210. }
  1211. table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
  1212. buf = pccb->pdata;
  1213. i = table_length;
  1214. while (--i) {
  1215. prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
  1216. MAX_PRDT_ENTRY - 1);
  1217. buf += MAX_PRDT_ENTRY;
  1218. datalen -= MAX_PRDT_ENTRY;
  1219. }
  1220. prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
  1221. req_desc->prd_table_length = table_length;
  1222. }
  1223. static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
  1224. {
  1225. struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
  1226. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  1227. u32 upiu_flags;
  1228. int ocs, result = 0;
  1229. u8 scsi_status;
  1230. ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
  1231. ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
  1232. prepare_prdt_table(hba, pccb);
  1233. ufshcd_send_command(hba, TASK_TAG);
  1234. ocs = ufshcd_get_tr_ocs(hba);
  1235. switch (ocs) {
  1236. case OCS_SUCCESS:
  1237. result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
  1238. switch (result) {
  1239. case UPIU_TRANSACTION_RESPONSE:
  1240. result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
  1241. scsi_status = result & MASK_SCSI_STATUS;
  1242. if (scsi_status)
  1243. return -EINVAL;
  1244. break;
  1245. case UPIU_TRANSACTION_REJECT_UPIU:
  1246. /* TODO: handle Reject UPIU Response */
  1247. dev_err(hba->dev,
  1248. "Reject UPIU not fully implemented\n");
  1249. return -EINVAL;
  1250. default:
  1251. dev_err(hba->dev,
  1252. "Unexpected request response code = %x\n",
  1253. result);
  1254. return -EINVAL;
  1255. }
  1256. break;
  1257. default:
  1258. dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
  1259. return -EINVAL;
  1260. }
  1261. return 0;
  1262. }
  1263. static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
  1264. int desc_index, u8 *buf, u32 size)
  1265. {
  1266. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  1267. }
  1268. static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  1269. {
  1270. return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
  1271. }
  1272. /**
  1273. * ufshcd_read_string_desc - read string descriptor
  1274. *
  1275. */
  1276. int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
  1277. u8 *buf, u32 size, bool ascii)
  1278. {
  1279. int err = 0;
  1280. err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
  1281. size);
  1282. if (err) {
  1283. dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
  1284. __func__, QUERY_REQ_RETRIES, err);
  1285. goto out;
  1286. }
  1287. if (ascii) {
  1288. int desc_len;
  1289. int ascii_len;
  1290. int i;
  1291. u8 *buff_ascii;
  1292. desc_len = buf[0];
  1293. /* remove header and divide by 2 to move from UTF16 to UTF8 */
  1294. ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
  1295. if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
  1296. dev_err(hba->dev, "%s: buffer allocated size is too small\n",
  1297. __func__);
  1298. err = -ENOMEM;
  1299. goto out;
  1300. }
  1301. buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
  1302. if (!buff_ascii) {
  1303. err = -ENOMEM;
  1304. goto out;
  1305. }
  1306. /*
  1307. * the descriptor contains string in UTF16 format
  1308. * we need to convert to utf-8 so it can be displayed
  1309. */
  1310. utf16_to_utf8(buff_ascii,
  1311. (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
  1312. /* replace non-printable or non-ASCII characters with spaces */
  1313. for (i = 0; i < ascii_len; i++)
  1314. ufshcd_remove_non_printable(&buff_ascii[i]);
  1315. memset(buf + QUERY_DESC_HDR_SIZE, 0,
  1316. size - QUERY_DESC_HDR_SIZE);
  1317. memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
  1318. buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
  1319. kfree(buff_ascii);
  1320. }
  1321. out:
  1322. return err;
  1323. }
  1324. static int ufs_get_device_desc(struct ufs_hba *hba,
  1325. struct ufs_dev_desc *dev_desc)
  1326. {
  1327. int err;
  1328. size_t buff_len;
  1329. u8 model_index;
  1330. u8 *desc_buf;
  1331. buff_len = max_t(size_t, hba->desc_size.dev_desc,
  1332. QUERY_DESC_MAX_SIZE + 1);
  1333. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1334. if (!desc_buf) {
  1335. err = -ENOMEM;
  1336. goto out;
  1337. }
  1338. err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
  1339. if (err) {
  1340. dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
  1341. __func__, err);
  1342. goto out;
  1343. }
  1344. /*
  1345. * getting vendor (manufacturerID) and Bank Index in big endian
  1346. * format
  1347. */
  1348. dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
  1349. desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
  1350. model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
  1351. /* Zero-pad entire buffer for string termination. */
  1352. memset(desc_buf, 0, buff_len);
  1353. err = ufshcd_read_string_desc(hba, model_index, desc_buf,
  1354. QUERY_DESC_MAX_SIZE, true/*ASCII*/);
  1355. if (err) {
  1356. dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
  1357. __func__, err);
  1358. goto out;
  1359. }
  1360. desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
  1361. strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
  1362. min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
  1363. MAX_MODEL_LEN));
  1364. /* Null terminate the model string */
  1365. dev_desc->model[MAX_MODEL_LEN] = '\0';
  1366. out:
  1367. kfree(desc_buf);
  1368. return err;
  1369. }
  1370. /**
  1371. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  1372. */
  1373. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  1374. {
  1375. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  1376. if (hba->max_pwr_info.is_valid)
  1377. return 0;
  1378. pwr_info->pwr_tx = FAST_MODE;
  1379. pwr_info->pwr_rx = FAST_MODE;
  1380. pwr_info->hs_rate = PA_HS_MODE_B;
  1381. /* Get the connected lane count */
  1382. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  1383. &pwr_info->lane_rx);
  1384. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  1385. &pwr_info->lane_tx);
  1386. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  1387. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  1388. __func__, pwr_info->lane_rx, pwr_info->lane_tx);
  1389. return -EINVAL;
  1390. }
  1391. /*
  1392. * First, get the maximum gears of HS speed.
  1393. * If a zero value, it means there is no HSGEAR capability.
  1394. * Then, get the maximum gears of PWM speed.
  1395. */
  1396. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  1397. if (!pwr_info->gear_rx) {
  1398. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  1399. &pwr_info->gear_rx);
  1400. if (!pwr_info->gear_rx) {
  1401. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  1402. __func__, pwr_info->gear_rx);
  1403. return -EINVAL;
  1404. }
  1405. pwr_info->pwr_rx = SLOW_MODE;
  1406. }
  1407. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  1408. &pwr_info->gear_tx);
  1409. if (!pwr_info->gear_tx) {
  1410. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  1411. &pwr_info->gear_tx);
  1412. if (!pwr_info->gear_tx) {
  1413. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  1414. __func__, pwr_info->gear_tx);
  1415. return -EINVAL;
  1416. }
  1417. pwr_info->pwr_tx = SLOW_MODE;
  1418. }
  1419. hba->max_pwr_info.is_valid = true;
  1420. return 0;
  1421. }
  1422. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  1423. struct ufs_pa_layer_attr *pwr_mode)
  1424. {
  1425. int ret;
  1426. /* if already configured to the requested pwr_mode */
  1427. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  1428. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  1429. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  1430. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  1431. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  1432. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  1433. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  1434. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  1435. return 0;
  1436. }
  1437. /*
  1438. * Configure attributes for power mode change with below.
  1439. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  1440. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  1441. * - PA_HSSERIES
  1442. */
  1443. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  1444. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  1445. pwr_mode->lane_rx);
  1446. if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
  1447. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  1448. else
  1449. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  1450. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  1451. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  1452. pwr_mode->lane_tx);
  1453. if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
  1454. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  1455. else
  1456. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  1457. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  1458. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  1459. pwr_mode->pwr_rx == FAST_MODE ||
  1460. pwr_mode->pwr_tx == FAST_MODE)
  1461. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  1462. pwr_mode->hs_rate);
  1463. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
  1464. pwr_mode->pwr_tx);
  1465. if (ret) {
  1466. dev_err(hba->dev,
  1467. "%s: power mode change failed %d\n", __func__, ret);
  1468. return ret;
  1469. }
  1470. /* Copy new Power Mode to power info */
  1471. memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
  1472. return ret;
  1473. }
  1474. /**
  1475. * ufshcd_verify_dev_init() - Verify device initialization
  1476. *
  1477. */
  1478. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  1479. {
  1480. int retries;
  1481. int err;
  1482. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  1483. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  1484. NOP_OUT_TIMEOUT);
  1485. if (!err || err == -ETIMEDOUT)
  1486. break;
  1487. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  1488. }
  1489. if (err)
  1490. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  1491. return err;
  1492. }
  1493. /**
  1494. * ufshcd_complete_dev_init() - checks device readiness
  1495. */
  1496. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  1497. {
  1498. int i;
  1499. int err;
  1500. bool flag_res = 1;
  1501. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  1502. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  1503. if (err) {
  1504. dev_err(hba->dev,
  1505. "%s setting fDeviceInit flag failed with error %d\n",
  1506. __func__, err);
  1507. goto out;
  1508. }
  1509. /* poll for max. 1000 iterations for fDeviceInit flag to clear */
  1510. for (i = 0; i < 1000 && !err && flag_res; i++)
  1511. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  1512. QUERY_FLAG_IDN_FDEVICEINIT,
  1513. &flag_res);
  1514. if (err)
  1515. dev_err(hba->dev,
  1516. "%s reading fDeviceInit flag failed with error %d\n",
  1517. __func__, err);
  1518. else if (flag_res)
  1519. dev_err(hba->dev,
  1520. "%s fDeviceInit was not cleared by the device\n",
  1521. __func__);
  1522. out:
  1523. return err;
  1524. }
  1525. static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
  1526. {
  1527. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  1528. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  1529. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  1530. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  1531. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  1532. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  1533. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  1534. }
  1535. int ufs_start(struct ufs_hba *hba)
  1536. {
  1537. struct ufs_dev_desc card = {0};
  1538. int ret;
  1539. ret = ufshcd_link_startup(hba);
  1540. if (ret)
  1541. return ret;
  1542. ret = ufshcd_verify_dev_init(hba);
  1543. if (ret)
  1544. return ret;
  1545. ret = ufshcd_complete_dev_init(hba);
  1546. if (ret)
  1547. return ret;
  1548. /* Init check for device descriptor sizes */
  1549. ufshcd_init_desc_sizes(hba);
  1550. ret = ufs_get_device_desc(hba, &card);
  1551. if (ret) {
  1552. dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
  1553. __func__, ret);
  1554. return ret;
  1555. }
  1556. if (ufshcd_get_max_pwr_mode(hba)) {
  1557. dev_err(hba->dev,
  1558. "%s: Failed getting max supported power mode\n",
  1559. __func__);
  1560. } else {
  1561. ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
  1562. if (ret) {
  1563. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  1564. __func__, ret);
  1565. return ret;
  1566. }
  1567. printf("Device at %s up at:", hba->dev->name);
  1568. ufshcd_print_pwr_info(hba);
  1569. }
  1570. return 0;
  1571. }
  1572. int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
  1573. {
  1574. struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
  1575. struct scsi_platdata *scsi_plat;
  1576. struct udevice *scsi_dev;
  1577. int err;
  1578. device_find_first_child(ufs_dev, &scsi_dev);
  1579. if (!scsi_dev)
  1580. return -ENODEV;
  1581. scsi_plat = dev_get_uclass_platdata(scsi_dev);
  1582. scsi_plat->max_id = UFSHCD_MAX_ID;
  1583. scsi_plat->max_lun = UFS_MAX_LUNS;
  1584. scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
  1585. hba->dev = ufs_dev;
  1586. hba->ops = hba_ops;
  1587. hba->mmio_base = (void *)dev_read_addr(ufs_dev);
  1588. /* Set descriptor lengths to specification defaults */
  1589. ufshcd_def_desc_sizes(hba);
  1590. ufshcd_ops_init(hba);
  1591. /* Read capabilties registers */
  1592. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  1593. /* Get UFS version supported by the controller */
  1594. hba->version = ufshcd_get_ufs_version(hba);
  1595. if (hba->version != UFSHCI_VERSION_10 &&
  1596. hba->version != UFSHCI_VERSION_11 &&
  1597. hba->version != UFSHCI_VERSION_20 &&
  1598. hba->version != UFSHCI_VERSION_21)
  1599. dev_err(hba->dev, "invalid UFS version 0x%x\n",
  1600. hba->version);
  1601. /* Get Interrupt bit mask per version */
  1602. hba->intr_mask = ufshcd_get_intr_mask(hba);
  1603. /* Allocate memory for host memory space */
  1604. err = ufshcd_memory_alloc(hba);
  1605. if (err) {
  1606. dev_err(hba->dev, "Memory allocation failed\n");
  1607. return err;
  1608. }
  1609. /* Configure Local data structures */
  1610. ufshcd_host_memory_configure(hba);
  1611. /*
  1612. * In order to avoid any spurious interrupt immediately after
  1613. * registering UFS controller interrupt handler, clear any pending UFS
  1614. * interrupt status and disable all the UFS interrupts.
  1615. */
  1616. ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
  1617. REG_INTERRUPT_STATUS);
  1618. ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
  1619. err = ufshcd_hba_enable(hba);
  1620. if (err) {
  1621. dev_err(hba->dev, "Host controller enable failed\n");
  1622. return err;
  1623. }
  1624. err = ufs_start(hba);
  1625. if (err)
  1626. return err;
  1627. return 0;
  1628. }
  1629. int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
  1630. {
  1631. int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
  1632. scsi_devp);
  1633. return ret;
  1634. }
  1635. static struct scsi_ops ufs_ops = {
  1636. .exec = ufs_scsi_exec,
  1637. };
  1638. int ufs_probe_dev(int index)
  1639. {
  1640. struct udevice *dev;
  1641. return uclass_get_device(UCLASS_UFS, index, &dev);
  1642. }
  1643. int ufs_probe(void)
  1644. {
  1645. struct udevice *dev;
  1646. int ret, i;
  1647. for (i = 0;; i++) {
  1648. ret = uclass_get_device(UCLASS_UFS, i, &dev);
  1649. if (ret == -ENODEV)
  1650. break;
  1651. }
  1652. return 0;
  1653. }
  1654. U_BOOT_DRIVER(ufs_scsi) = {
  1655. .id = UCLASS_SCSI,
  1656. .name = "ufs_scsi",
  1657. .ops = &ufs_ops,
  1658. };