ftmac110.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday 10/100Mbps Ethernet Controller
  4. *
  5. * (C) Copyright 2013 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <malloc.h>
  11. #include <net.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <linux/dma-mapping.h>
  15. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  16. #include <miiphy.h>
  17. #endif
  18. #include "ftmac110.h"
  19. #define CFG_RXDES_NUM 8
  20. #define CFG_TXDES_NUM 2
  21. #define CFG_XBUF_SIZE 1536
  22. #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  23. #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  24. #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
  25. /*
  26. * FTMAC110 DMA design issue
  27. *
  28. * Its DMA engine has a weird restriction that its Rx DMA engine
  29. * accepts only 16-bits aligned address, 32-bits aligned is not
  30. * acceptable. However this restriction does not apply to Tx DMA.
  31. *
  32. * Conclusion:
  33. * (1) Tx DMA Buffer Address:
  34. * 1 bytes aligned: Invalid
  35. * 2 bytes aligned: O.K
  36. * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
  37. * (2) Rx DMA Buffer Address:
  38. * 1 bytes aligned: Invalid
  39. * 2 bytes aligned: O.K
  40. * 4 bytes aligned: Invalid
  41. */
  42. struct ftmac110_chip {
  43. void __iomem *regs;
  44. uint32_t imr;
  45. uint32_t maccr;
  46. uint32_t lnkup;
  47. uint32_t phy_addr;
  48. struct ftmac110_desc *rxd;
  49. ulong rxd_dma;
  50. uint32_t rxd_idx;
  51. struct ftmac110_desc *txd;
  52. ulong txd_dma;
  53. uint32_t txd_idx;
  54. };
  55. static int ftmac110_reset(struct eth_device *dev);
  56. static uint16_t mdio_read(struct eth_device *dev,
  57. uint8_t phyaddr, uint8_t phyreg)
  58. {
  59. struct ftmac110_chip *chip = dev->priv;
  60. struct ftmac110_regs *regs = chip->regs;
  61. uint32_t tmp, ts;
  62. uint16_t ret = 0xffff;
  63. tmp = PHYCR_READ
  64. | (phyaddr << PHYCR_ADDR_SHIFT)
  65. | (phyreg << PHYCR_REG_SHIFT);
  66. writel(tmp, &regs->phycr);
  67. for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
  68. tmp = readl(&regs->phycr);
  69. if (tmp & PHYCR_READ)
  70. continue;
  71. break;
  72. }
  73. if (tmp & PHYCR_READ)
  74. printf("ftmac110: mdio read timeout\n");
  75. else
  76. ret = (uint16_t)(tmp & 0xffff);
  77. return ret;
  78. }
  79. static void mdio_write(struct eth_device *dev,
  80. uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
  81. {
  82. struct ftmac110_chip *chip = dev->priv;
  83. struct ftmac110_regs *regs = chip->regs;
  84. uint32_t tmp, ts;
  85. tmp = PHYCR_WRITE
  86. | (phyaddr << PHYCR_ADDR_SHIFT)
  87. | (phyreg << PHYCR_REG_SHIFT);
  88. writel(phydata, &regs->phydr);
  89. writel(tmp, &regs->phycr);
  90. for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
  91. if (readl(&regs->phycr) & PHYCR_WRITE)
  92. continue;
  93. break;
  94. }
  95. if (readl(&regs->phycr) & PHYCR_WRITE)
  96. printf("ftmac110: mdio write timeout\n");
  97. }
  98. static uint32_t ftmac110_phyqry(struct eth_device *dev)
  99. {
  100. ulong ts;
  101. uint32_t maccr;
  102. uint16_t pa, tmp, bmsr, bmcr;
  103. struct ftmac110_chip *chip = dev->priv;
  104. /* Default = 100Mbps Full */
  105. maccr = MACCR_100M | MACCR_FD;
  106. /* 1. find the phy device */
  107. for (pa = 0; pa < 32; ++pa) {
  108. tmp = mdio_read(dev, pa, MII_PHYSID1);
  109. if (tmp == 0xFFFF || tmp == 0x0000)
  110. continue;
  111. chip->phy_addr = pa;
  112. break;
  113. }
  114. if (pa >= 32) {
  115. puts("ftmac110: phy device not found!\n");
  116. goto exit;
  117. }
  118. /* 2. wait until link-up & auto-negotiation complete */
  119. chip->lnkup = 0;
  120. bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
  121. ts = get_timer(0);
  122. do {
  123. bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
  124. chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
  125. if (!chip->lnkup)
  126. continue;
  127. if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
  128. break;
  129. } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
  130. if (!chip->lnkup) {
  131. puts("ftmac110: link down\n");
  132. goto exit;
  133. }
  134. if (!(bmcr & BMCR_ANENABLE))
  135. puts("ftmac110: auto negotiation disabled\n");
  136. else if (!(bmsr & BMSR_ANEGCOMPLETE))
  137. puts("ftmac110: auto negotiation timeout\n");
  138. /* 3. derive MACCR */
  139. if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
  140. tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
  141. tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
  142. if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
  143. maccr = MACCR_100M | MACCR_FD;
  144. else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
  145. maccr = MACCR_100M;
  146. else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
  147. maccr = MACCR_FD;
  148. else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
  149. maccr = 0;
  150. } else {
  151. if (bmcr & BMCR_SPEED100)
  152. maccr = MACCR_100M;
  153. else
  154. maccr = 0;
  155. if (bmcr & BMCR_FULLDPLX)
  156. maccr |= MACCR_FD;
  157. }
  158. exit:
  159. printf("ftmac110: %d Mbps, %s\n",
  160. (maccr & MACCR_100M) ? 100 : 10,
  161. (maccr & MACCR_FD) ? "Full" : "half");
  162. return maccr;
  163. }
  164. static int ftmac110_reset(struct eth_device *dev)
  165. {
  166. uint8_t *a;
  167. uint32_t i, maccr;
  168. struct ftmac110_chip *chip = dev->priv;
  169. struct ftmac110_regs *regs = chip->regs;
  170. /* 1. MAC reset */
  171. writel(MACCR_RESET, &regs->maccr);
  172. for (i = get_timer(0); get_timer(i) < 1000; ) {
  173. if (readl(&regs->maccr) & MACCR_RESET)
  174. continue;
  175. break;
  176. }
  177. if (readl(&regs->maccr) & MACCR_RESET) {
  178. printf("ftmac110: reset failed\n");
  179. return -ENXIO;
  180. }
  181. /* 1-1. Init tx ring */
  182. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  183. /* owned by SW */
  184. chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
  185. }
  186. chip->txd_idx = 0;
  187. /* 1-2. Init rx ring */
  188. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  189. /* owned by HW */
  190. chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
  191. chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
  192. }
  193. chip->rxd_idx = 0;
  194. /* 2. PHY status query */
  195. maccr = ftmac110_phyqry(dev);
  196. /* 3. Fix up the MACCR value */
  197. chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
  198. | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
  199. /* 4. MAC address setup */
  200. a = dev->enetaddr;
  201. writel(a[1] | (a[0] << 8), &regs->mac[0]);
  202. writel(a[5] | (a[4] << 8) | (a[3] << 16)
  203. | (a[2] << 24), &regs->mac[1]);
  204. /* 5. MAC registers setup */
  205. writel(chip->rxd_dma, &regs->rxba);
  206. writel(chip->txd_dma, &regs->txba);
  207. /* interrupt at each tx/rx */
  208. writel(ITC_DEFAULT, &regs->itc);
  209. /* no tx pool, rx poll = 1 normal cycle */
  210. writel(APTC_DEFAULT, &regs->aptc);
  211. /* rx threshold = [6/8 fifo, 2/8 fifo] */
  212. writel(DBLAC_DEFAULT, &regs->dblac);
  213. /* disable & clear all interrupt status */
  214. chip->imr = 0;
  215. writel(ISR_ALL, &regs->isr);
  216. writel(chip->imr, &regs->imr);
  217. /* enable mac */
  218. writel(chip->maccr, &regs->maccr);
  219. return 0;
  220. }
  221. static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
  222. {
  223. debug("ftmac110: probe\n");
  224. if (ftmac110_reset(dev))
  225. return -1;
  226. return 0;
  227. }
  228. static void ftmac110_halt(struct eth_device *dev)
  229. {
  230. struct ftmac110_chip *chip = dev->priv;
  231. struct ftmac110_regs *regs = chip->regs;
  232. writel(0, &regs->imr);
  233. writel(0, &regs->maccr);
  234. debug("ftmac110: halt\n");
  235. }
  236. static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
  237. {
  238. struct ftmac110_chip *chip = dev->priv;
  239. struct ftmac110_regs *regs = chip->regs;
  240. struct ftmac110_desc *txd;
  241. uint64_t ctrl;
  242. if (!chip->lnkup)
  243. return 0;
  244. if (len <= 0 || len > CFG_XBUF_SIZE) {
  245. printf("ftmac110: bad tx pkt len(%d)\n", len);
  246. return 0;
  247. }
  248. len = max(60, len);
  249. txd = &chip->txd[chip->txd_idx];
  250. ctrl = le64_to_cpu(txd->ctrl);
  251. if (ctrl & FTMAC110_TXD_OWNER) {
  252. /* kick-off Tx DMA */
  253. writel(0xffffffff, &regs->txpd);
  254. printf("ftmac110: out of txd\n");
  255. return 0;
  256. }
  257. memcpy(txd->vbuf, (void *)pkt, len);
  258. dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
  259. /* clear control bits */
  260. ctrl &= FTMAC110_TXD_CLRMASK;
  261. /* set len, fts and lts */
  262. ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
  263. /* set owner bit */
  264. ctrl |= FTMAC110_TXD_OWNER;
  265. /* write back to descriptor */
  266. txd->ctrl = cpu_to_le64(ctrl);
  267. /* kick-off Tx DMA */
  268. writel(0xffffffff, &regs->txpd);
  269. chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
  270. return len;
  271. }
  272. static int ftmac110_recv(struct eth_device *dev)
  273. {
  274. struct ftmac110_chip *chip = dev->priv;
  275. struct ftmac110_desc *rxd;
  276. uint32_t len, rlen = 0;
  277. uint64_t ctrl;
  278. uint8_t *buf;
  279. if (!chip->lnkup)
  280. return 0;
  281. do {
  282. rxd = &chip->rxd[chip->rxd_idx];
  283. ctrl = le64_to_cpu(rxd->ctrl);
  284. if (ctrl & FTMAC110_RXD_OWNER)
  285. break;
  286. len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
  287. buf = rxd->vbuf;
  288. if (ctrl & FTMAC110_RXD_ERRMASK) {
  289. printf("ftmac110: rx error\n");
  290. } else {
  291. dma_map_single(buf, len, DMA_FROM_DEVICE);
  292. net_process_received_packet(buf, len);
  293. rlen += len;
  294. }
  295. /* owned by hardware */
  296. ctrl &= FTMAC110_RXD_CLRMASK;
  297. ctrl |= FTMAC110_RXD_OWNER;
  298. rxd->ctrl |= cpu_to_le64(ctrl);
  299. chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
  300. } while (0);
  301. return rlen;
  302. }
  303. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  304. static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
  305. int reg)
  306. {
  307. uint16_t value = 0;
  308. int ret = 0;
  309. struct eth_device *dev;
  310. dev = eth_get_dev_by_name(bus->name);
  311. if (dev == NULL) {
  312. printf("%s: no such device\n", bus->name);
  313. ret = -1;
  314. } else {
  315. value = mdio_read(dev, addr, reg);
  316. }
  317. if (ret < 0)
  318. return ret;
  319. return value;
  320. }
  321. static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
  322. int reg, u16 value)
  323. {
  324. int ret = 0;
  325. struct eth_device *dev;
  326. dev = eth_get_dev_by_name(bus->name);
  327. if (dev == NULL) {
  328. printf("%s: no such device\n", bus->name);
  329. ret = -1;
  330. } else {
  331. mdio_write(dev, addr, reg, value);
  332. }
  333. return ret;
  334. }
  335. #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
  336. int ftmac110_initialize(bd_t *bis)
  337. {
  338. int i, card_nr = 0;
  339. struct eth_device *dev;
  340. struct ftmac110_chip *chip;
  341. dev = malloc(sizeof(*dev) + sizeof(*chip));
  342. if (dev == NULL) {
  343. panic("ftmac110: out of memory 1\n");
  344. return -1;
  345. }
  346. chip = (struct ftmac110_chip *)(dev + 1);
  347. memset(dev, 0, sizeof(*dev) + sizeof(*chip));
  348. sprintf(dev->name, "FTMAC110#%d", card_nr);
  349. dev->iobase = CONFIG_FTMAC110_BASE;
  350. chip->regs = (void __iomem *)dev->iobase;
  351. dev->priv = chip;
  352. dev->init = ftmac110_probe;
  353. dev->halt = ftmac110_halt;
  354. dev->send = ftmac110_send;
  355. dev->recv = ftmac110_recv;
  356. /* allocate tx descriptors (it must be 16 bytes aligned) */
  357. chip->txd = dma_alloc_coherent(
  358. sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
  359. if (!chip->txd)
  360. panic("ftmac110: out of memory 3\n");
  361. memset(chip->txd, 0,
  362. sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
  363. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  364. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
  365. if (!va)
  366. panic("ftmac110: out of memory 4\n");
  367. chip->txd[i].vbuf = va;
  368. chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
  369. chip->txd[i].ctrl = 0; /* owned by SW */
  370. }
  371. chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
  372. chip->txd_idx = 0;
  373. /* allocate rx descriptors (it must be 16 bytes aligned) */
  374. chip->rxd = dma_alloc_coherent(
  375. sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
  376. if (!chip->rxd)
  377. panic("ftmac110: out of memory 4\n");
  378. memset((void *)chip->rxd, 0,
  379. sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
  380. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  381. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
  382. if (!va)
  383. panic("ftmac110: out of memory 5\n");
  384. /* it needs to be exactly 2 bytes aligned */
  385. va = ((uint8_t *)va + 2);
  386. chip->rxd[i].vbuf = va;
  387. chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
  388. chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
  389. | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
  390. }
  391. chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
  392. chip->rxd_idx = 0;
  393. eth_register(dev);
  394. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  395. int retval;
  396. struct mii_dev *mdiodev = mdio_alloc();
  397. if (!mdiodev)
  398. return -ENOMEM;
  399. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  400. mdiodev->read = ftmac110_mdio_read;
  401. mdiodev->write = ftmac110_mdio_write;
  402. retval = mdio_register(mdiodev);
  403. if (retval < 0)
  404. return retval;
  405. #endif
  406. card_nr++;
  407. return card_nr;
  408. }