altera_tse.c 18 KB

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  1. /*
  2. * Altera 10/100/1000 triple speed ethernet mac driver
  3. *
  4. * Copyright (C) 2008 Altera Corporation.
  5. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <fdt_support.h>
  16. #include <memalign.h>
  17. #include <miiphy.h>
  18. #include <net.h>
  19. #include <asm/cache.h>
  20. #include <linux/dma-mapping.h>
  21. #include <asm/io.h>
  22. #include "altera_tse.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. static inline void alt_sgdma_construct_descriptor(
  25. struct alt_sgdma_descriptor *desc,
  26. struct alt_sgdma_descriptor *next,
  27. void *read_addr,
  28. void *write_addr,
  29. u16 length_or_eop,
  30. int generate_eop,
  31. int read_fixed,
  32. int write_fixed_or_sop)
  33. {
  34. u8 val;
  35. /*
  36. * Mark the "next" descriptor as "not" owned by hardware. This prevents
  37. * The SGDMA controller from continuing to process the chain.
  38. */
  39. next->descriptor_control = next->descriptor_control &
  40. ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  41. memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
  42. desc->source = virt_to_phys(read_addr);
  43. desc->destination = virt_to_phys(write_addr);
  44. desc->next = virt_to_phys(next);
  45. desc->bytes_to_transfer = length_or_eop;
  46. /*
  47. * Set the descriptor control block as follows:
  48. * - Set "owned by hardware" bit
  49. * - Optionally set "generate EOP" bit
  50. * - Optionally set the "read from fixed address" bit
  51. * - Optionally set the "write to fixed address bit (which serves
  52. * serves as a "generate SOP" control bit in memory-to-stream mode).
  53. * - Set the 4-bit atlantic channel, if specified
  54. *
  55. * Note this step is performed after all other descriptor information
  56. * has been filled out so that, if the controller already happens to be
  57. * pointing at this descriptor, it will not run (via the "owned by
  58. * hardware" bit) until all other descriptor has been set up.
  59. */
  60. val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  61. if (generate_eop)
  62. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
  63. if (read_fixed)
  64. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
  65. if (write_fixed_or_sop)
  66. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
  67. desc->descriptor_control = val;
  68. }
  69. static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
  70. {
  71. int status;
  72. ulong ctime;
  73. /* Wait for the descriptor (chain) to complete */
  74. ctime = get_timer(0);
  75. while (1) {
  76. status = readl(&regs->status);
  77. if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
  78. break;
  79. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  80. status = -ETIMEDOUT;
  81. debug("sgdma timeout\n");
  82. break;
  83. }
  84. }
  85. /* Clear Run */
  86. writel(0, &regs->control);
  87. /* Clear status */
  88. writel(0xff, &regs->status);
  89. return status;
  90. }
  91. static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
  92. struct alt_sgdma_descriptor *desc)
  93. {
  94. u32 val;
  95. /* Point the controller at the descriptor */
  96. writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
  97. /*
  98. * Set up SGDMA controller to:
  99. * - Disable interrupt generation
  100. * - Run once a valid descriptor is written to controller
  101. * - Stop on an error with any particular descriptor
  102. */
  103. val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
  104. writel(val, &regs->control);
  105. return 0;
  106. }
  107. static void tse_adjust_link(struct altera_tse_priv *priv,
  108. struct phy_device *phydev)
  109. {
  110. struct alt_tse_mac *mac_dev = priv->mac_dev;
  111. u32 refvar;
  112. if (!phydev->link) {
  113. debug("%s: No link.\n", phydev->dev->name);
  114. return;
  115. }
  116. refvar = readl(&mac_dev->command_config);
  117. if (phydev->duplex)
  118. refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
  119. else
  120. refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
  121. switch (phydev->speed) {
  122. case 1000:
  123. refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
  124. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  125. break;
  126. case 100:
  127. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  128. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  129. break;
  130. case 10:
  131. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  132. refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
  133. break;
  134. }
  135. writel(refvar, &mac_dev->command_config);
  136. }
  137. static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
  138. {
  139. struct altera_tse_priv *priv = dev_get_priv(dev);
  140. struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
  141. alt_sgdma_construct_descriptor(
  142. tx_desc,
  143. tx_desc + 1,
  144. packet, /* read addr */
  145. NULL, /* write addr */
  146. length, /* length or EOP ,will change for each tx */
  147. 1, /* gen eop */
  148. 0, /* read fixed */
  149. 1 /* write fixed or sop */
  150. );
  151. /* send the packet */
  152. alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
  153. alt_sgdma_wait_transfer(priv->sgdma_tx);
  154. debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
  155. return tx_desc->actual_bytes_transferred;
  156. }
  157. static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
  158. uchar **packetp)
  159. {
  160. struct altera_tse_priv *priv = dev_get_priv(dev);
  161. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  162. int packet_length;
  163. if (rx_desc->descriptor_status &
  164. ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
  165. alt_sgdma_wait_transfer(priv->sgdma_rx);
  166. packet_length = rx_desc->actual_bytes_transferred;
  167. debug("recv %d bytes\n", packet_length);
  168. *packetp = priv->rx_buf;
  169. return packet_length;
  170. }
  171. return -EAGAIN;
  172. }
  173. static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
  174. int length)
  175. {
  176. struct altera_tse_priv *priv = dev_get_priv(dev);
  177. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  178. alt_sgdma_construct_descriptor(
  179. rx_desc,
  180. rx_desc + 1,
  181. NULL, /* read addr */
  182. priv->rx_buf, /* write addr */
  183. 0, /* length or EOP */
  184. 0, /* gen eop */
  185. 0, /* read fixed */
  186. 0 /* write fixed or sop */
  187. );
  188. /* setup the sgdma */
  189. alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
  190. debug("recv setup\n");
  191. return 0;
  192. }
  193. static void altera_tse_stop_mac(struct altera_tse_priv *priv)
  194. {
  195. struct alt_tse_mac *mac_dev = priv->mac_dev;
  196. u32 status;
  197. ulong ctime;
  198. /* reset the mac */
  199. writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
  200. ctime = get_timer(0);
  201. while (1) {
  202. status = readl(&mac_dev->command_config);
  203. if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
  204. break;
  205. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  206. debug("Reset mac timeout\n");
  207. break;
  208. }
  209. }
  210. }
  211. static void altera_tse_stop_sgdma(struct udevice *dev)
  212. {
  213. struct altera_tse_priv *priv = dev_get_priv(dev);
  214. struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
  215. struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
  216. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  217. int ret;
  218. /* clear rx desc & wait for sgdma to complete */
  219. rx_desc->descriptor_control = 0;
  220. writel(0, &rx_sgdma->control);
  221. ret = alt_sgdma_wait_transfer(rx_sgdma);
  222. if (ret == -ETIMEDOUT)
  223. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  224. &rx_sgdma->control);
  225. writel(0, &tx_sgdma->control);
  226. ret = alt_sgdma_wait_transfer(tx_sgdma);
  227. if (ret == -ETIMEDOUT)
  228. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  229. &tx_sgdma->control);
  230. }
  231. static void msgdma_reset(struct msgdma_csr *csr)
  232. {
  233. u32 status;
  234. ulong ctime;
  235. /* Reset mSGDMA */
  236. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  237. writel(MSGDMA_CSR_CTL_RESET, &csr->control);
  238. ctime = get_timer(0);
  239. while (1) {
  240. status = readl(&csr->status);
  241. if (!(status & MSGDMA_CSR_STAT_RESETTING))
  242. break;
  243. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  244. debug("Reset msgdma timeout\n");
  245. break;
  246. }
  247. }
  248. /* Clear status */
  249. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  250. }
  251. static u32 msgdma_wait(struct msgdma_csr *csr)
  252. {
  253. u32 status;
  254. ulong ctime;
  255. /* Wait for the descriptor to complete */
  256. ctime = get_timer(0);
  257. while (1) {
  258. status = readl(&csr->status);
  259. if (!(status & MSGDMA_CSR_STAT_BUSY))
  260. break;
  261. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  262. debug("sgdma timeout\n");
  263. break;
  264. }
  265. }
  266. /* Clear status */
  267. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  268. return status;
  269. }
  270. static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
  271. int length)
  272. {
  273. struct altera_tse_priv *priv = dev_get_priv(dev);
  274. struct msgdma_extended_desc *desc = priv->tx_desc;
  275. u32 tx_buf = virt_to_phys(packet);
  276. u32 status;
  277. writel(tx_buf, &desc->read_addr_lo);
  278. writel(0, &desc->read_addr_hi);
  279. writel(0, &desc->write_addr_lo);
  280. writel(0, &desc->write_addr_hi);
  281. writel(length, &desc->len);
  282. writel(0, &desc->burst_seq_num);
  283. writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
  284. writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
  285. status = msgdma_wait(priv->sgdma_tx);
  286. debug("sent %d bytes, status %08x\n", length, status);
  287. return 0;
  288. }
  289. static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
  290. uchar **packetp)
  291. {
  292. struct altera_tse_priv *priv = dev_get_priv(dev);
  293. struct msgdma_csr *csr = priv->sgdma_rx;
  294. struct msgdma_response *resp = priv->rx_resp;
  295. u32 level, length, status;
  296. level = readl(&csr->resp_fill_level);
  297. if (level & 0xffff) {
  298. length = readl(&resp->bytes_transferred);
  299. status = readl(&resp->status);
  300. debug("recv %d bytes, status %08x\n", length, status);
  301. *packetp = priv->rx_buf;
  302. return length;
  303. }
  304. return -EAGAIN;
  305. }
  306. static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
  307. int length)
  308. {
  309. struct altera_tse_priv *priv = dev_get_priv(dev);
  310. struct msgdma_extended_desc *desc = priv->rx_desc;
  311. u32 rx_buf = virt_to_phys(priv->rx_buf);
  312. writel(0, &desc->read_addr_lo);
  313. writel(0, &desc->read_addr_hi);
  314. writel(rx_buf, &desc->write_addr_lo);
  315. writel(0, &desc->write_addr_hi);
  316. writel(PKTSIZE_ALIGN, &desc->len);
  317. writel(0, &desc->burst_seq_num);
  318. writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
  319. writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
  320. debug("recv setup\n");
  321. return 0;
  322. }
  323. static void altera_tse_stop_msgdma(struct udevice *dev)
  324. {
  325. struct altera_tse_priv *priv = dev_get_priv(dev);
  326. msgdma_reset(priv->sgdma_rx);
  327. msgdma_reset(priv->sgdma_tx);
  328. }
  329. static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  330. {
  331. struct altera_tse_priv *priv = bus->priv;
  332. struct alt_tse_mac *mac_dev = priv->mac_dev;
  333. u32 value;
  334. /* set mdio address */
  335. writel(addr, &mac_dev->mdio_phy1_addr);
  336. /* get the data */
  337. value = readl(&mac_dev->mdio_phy1[reg]);
  338. return value & 0xffff;
  339. }
  340. static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  341. u16 val)
  342. {
  343. struct altera_tse_priv *priv = bus->priv;
  344. struct alt_tse_mac *mac_dev = priv->mac_dev;
  345. /* set mdio address */
  346. writel(addr, &mac_dev->mdio_phy1_addr);
  347. /* set the data */
  348. writel(val, &mac_dev->mdio_phy1[reg]);
  349. return 0;
  350. }
  351. static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
  352. {
  353. struct mii_dev *bus = mdio_alloc();
  354. if (!bus) {
  355. printf("Failed to allocate MDIO bus\n");
  356. return -ENOMEM;
  357. }
  358. bus->read = tse_mdio_read;
  359. bus->write = tse_mdio_write;
  360. snprintf(bus->name, sizeof(bus->name), "%s", name);
  361. bus->priv = (void *)priv;
  362. return mdio_register(bus);
  363. }
  364. static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
  365. {
  366. struct phy_device *phydev;
  367. unsigned int mask = 0xffffffff;
  368. if (priv->phyaddr)
  369. mask = 1 << priv->phyaddr;
  370. phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
  371. if (!phydev)
  372. return -ENODEV;
  373. phy_connect_dev(phydev, dev);
  374. phydev->supported &= PHY_GBIT_FEATURES;
  375. phydev->advertising = phydev->supported;
  376. priv->phydev = phydev;
  377. phy_config(phydev);
  378. return 0;
  379. }
  380. static int altera_tse_write_hwaddr(struct udevice *dev)
  381. {
  382. struct altera_tse_priv *priv = dev_get_priv(dev);
  383. struct alt_tse_mac *mac_dev = priv->mac_dev;
  384. struct eth_pdata *pdata = dev_get_platdata(dev);
  385. u8 *hwaddr = pdata->enetaddr;
  386. u32 mac_lo, mac_hi;
  387. mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
  388. (hwaddr[1] << 8) | hwaddr[0];
  389. mac_hi = (hwaddr[5] << 8) | hwaddr[4];
  390. debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
  391. writel(mac_lo, &mac_dev->mac_addr_0);
  392. writel(mac_hi, &mac_dev->mac_addr_1);
  393. writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
  394. writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
  395. writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
  396. writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
  397. writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
  398. writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
  399. writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
  400. writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
  401. return 0;
  402. }
  403. static int altera_tse_send(struct udevice *dev, void *packet, int length)
  404. {
  405. struct altera_tse_priv *priv = dev_get_priv(dev);
  406. unsigned long tx_buf = (unsigned long)packet;
  407. flush_dcache_range(tx_buf, tx_buf + length);
  408. return priv->ops->send(dev, packet, length);
  409. }
  410. static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
  411. {
  412. struct altera_tse_priv *priv = dev_get_priv(dev);
  413. return priv->ops->recv(dev, flags, packetp);
  414. }
  415. static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
  416. int length)
  417. {
  418. struct altera_tse_priv *priv = dev_get_priv(dev);
  419. unsigned long rx_buf = (unsigned long)priv->rx_buf;
  420. invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
  421. return priv->ops->free_pkt(dev, packet, length);
  422. }
  423. static void altera_tse_stop(struct udevice *dev)
  424. {
  425. struct altera_tse_priv *priv = dev_get_priv(dev);
  426. priv->ops->stop(dev);
  427. altera_tse_stop_mac(priv);
  428. }
  429. static int altera_tse_start(struct udevice *dev)
  430. {
  431. struct altera_tse_priv *priv = dev_get_priv(dev);
  432. struct alt_tse_mac *mac_dev = priv->mac_dev;
  433. u32 val;
  434. int ret;
  435. /* need to create sgdma */
  436. debug("Configuring rx desc\n");
  437. altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
  438. /* start TSE */
  439. debug("Configuring TSE Mac\n");
  440. /* Initialize MAC registers */
  441. writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
  442. writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
  443. writel(0, &mac_dev->rx_sel_full_threshold);
  444. writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
  445. writel(0, &mac_dev->tx_sel_full_threshold);
  446. writel(8, &mac_dev->rx_almost_empty_threshold);
  447. writel(8, &mac_dev->rx_almost_full_threshold);
  448. writel(8, &mac_dev->tx_almost_empty_threshold);
  449. writel(3, &mac_dev->tx_almost_full_threshold);
  450. /* NO Shift */
  451. writel(0, &mac_dev->rx_cmd_stat);
  452. writel(0, &mac_dev->tx_cmd_stat);
  453. /* enable MAC */
  454. val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
  455. writel(val, &mac_dev->command_config);
  456. /* Start up the PHY */
  457. ret = phy_startup(priv->phydev);
  458. if (ret) {
  459. debug("Could not initialize PHY %s\n",
  460. priv->phydev->dev->name);
  461. return ret;
  462. }
  463. tse_adjust_link(priv, priv->phydev);
  464. if (!priv->phydev->link)
  465. return -EIO;
  466. return 0;
  467. }
  468. static const struct tse_ops tse_sgdma_ops = {
  469. .send = altera_tse_send_sgdma,
  470. .recv = altera_tse_recv_sgdma,
  471. .free_pkt = altera_tse_free_pkt_sgdma,
  472. .stop = altera_tse_stop_sgdma,
  473. };
  474. static const struct tse_ops tse_msgdma_ops = {
  475. .send = altera_tse_send_msgdma,
  476. .recv = altera_tse_recv_msgdma,
  477. .free_pkt = altera_tse_free_pkt_msgdma,
  478. .stop = altera_tse_stop_msgdma,
  479. };
  480. static int altera_tse_probe(struct udevice *dev)
  481. {
  482. struct eth_pdata *pdata = dev_get_platdata(dev);
  483. struct altera_tse_priv *priv = dev_get_priv(dev);
  484. void *blob = (void *)gd->fdt_blob;
  485. int node = dev_of_offset(dev);
  486. const char *list, *end;
  487. const fdt32_t *cell;
  488. void *base, *desc_mem = NULL;
  489. unsigned long addr, size;
  490. int parent, addrc, sizec;
  491. int len, idx;
  492. int ret;
  493. priv->dma_type = dev_get_driver_data(dev);
  494. if (priv->dma_type == ALT_SGDMA)
  495. priv->ops = &tse_sgdma_ops;
  496. else
  497. priv->ops = &tse_msgdma_ops;
  498. /*
  499. * decode regs. there are multiple reg tuples, and they need to
  500. * match with reg-names.
  501. */
  502. parent = fdt_parent_offset(blob, node);
  503. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  504. list = fdt_getprop(blob, node, "reg-names", &len);
  505. if (!list)
  506. return -ENOENT;
  507. end = list + len;
  508. cell = fdt_getprop(blob, node, "reg", &len);
  509. if (!cell)
  510. return -ENOENT;
  511. idx = 0;
  512. while (list < end) {
  513. addr = fdt_translate_address((void *)blob,
  514. node, cell + idx);
  515. size = fdt_addr_to_cpu(cell[idx + addrc]);
  516. base = map_physmem(addr, size, MAP_NOCACHE);
  517. len = strlen(list);
  518. if (strcmp(list, "control_port") == 0)
  519. priv->mac_dev = base;
  520. else if (strcmp(list, "rx_csr") == 0)
  521. priv->sgdma_rx = base;
  522. else if (strcmp(list, "rx_desc") == 0)
  523. priv->rx_desc = base;
  524. else if (strcmp(list, "rx_resp") == 0)
  525. priv->rx_resp = base;
  526. else if (strcmp(list, "tx_csr") == 0)
  527. priv->sgdma_tx = base;
  528. else if (strcmp(list, "tx_desc") == 0)
  529. priv->tx_desc = base;
  530. else if (strcmp(list, "s1") == 0)
  531. desc_mem = base;
  532. idx += addrc + sizec;
  533. list += (len + 1);
  534. }
  535. /* decode fifo depth */
  536. priv->rx_fifo_depth = fdtdec_get_int(blob, node,
  537. "rx-fifo-depth", 0);
  538. priv->tx_fifo_depth = fdtdec_get_int(blob, node,
  539. "tx-fifo-depth", 0);
  540. /* decode phy */
  541. addr = fdtdec_get_int(blob, node,
  542. "phy-handle", 0);
  543. addr = fdt_node_offset_by_phandle(blob, addr);
  544. priv->phyaddr = fdtdec_get_int(blob, addr,
  545. "reg", 0);
  546. /* init desc */
  547. if (priv->dma_type == ALT_SGDMA) {
  548. len = sizeof(struct alt_sgdma_descriptor) * 4;
  549. if (!desc_mem) {
  550. desc_mem = dma_alloc_coherent(len, &addr);
  551. if (!desc_mem)
  552. return -ENOMEM;
  553. }
  554. memset(desc_mem, 0, len);
  555. priv->tx_desc = desc_mem;
  556. priv->rx_desc = priv->tx_desc +
  557. 2 * sizeof(struct alt_sgdma_descriptor);
  558. }
  559. /* allocate recv packet buffer */
  560. priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
  561. if (!priv->rx_buf)
  562. return -ENOMEM;
  563. /* stop controller */
  564. debug("Reset TSE & SGDMAs\n");
  565. altera_tse_stop(dev);
  566. /* start the phy */
  567. priv->interface = pdata->phy_interface;
  568. tse_mdio_init(dev->name, priv);
  569. priv->bus = miiphy_get_dev_by_name(dev->name);
  570. ret = tse_phy_init(priv, dev);
  571. return ret;
  572. }
  573. static int altera_tse_ofdata_to_platdata(struct udevice *dev)
  574. {
  575. struct eth_pdata *pdata = dev_get_platdata(dev);
  576. const char *phy_mode;
  577. pdata->phy_interface = -1;
  578. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  579. NULL);
  580. if (phy_mode)
  581. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  582. if (pdata->phy_interface == -1) {
  583. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  584. return -EINVAL;
  585. }
  586. return 0;
  587. }
  588. static const struct eth_ops altera_tse_ops = {
  589. .start = altera_tse_start,
  590. .send = altera_tse_send,
  591. .recv = altera_tse_recv,
  592. .free_pkt = altera_tse_free_pkt,
  593. .stop = altera_tse_stop,
  594. .write_hwaddr = altera_tse_write_hwaddr,
  595. };
  596. static const struct udevice_id altera_tse_ids[] = {
  597. { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
  598. { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
  599. {}
  600. };
  601. U_BOOT_DRIVER(altera_tse) = {
  602. .name = "altera_tse",
  603. .id = UCLASS_ETH,
  604. .of_match = altera_tse_ids,
  605. .ops = &altera_tse_ops,
  606. .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
  607. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  608. .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
  609. .probe = altera_tse_probe,
  610. };