denali.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
  5. * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
  6. */
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <nand.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/devres.h>
  12. #include <linux/bitfield.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/io.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/rawnand.h>
  19. #include "denali.h"
  20. #define DENALI_NAND_NAME "denali-nand"
  21. /* for Indexed Addressing */
  22. #define DENALI_INDEXED_CTRL 0x00
  23. #define DENALI_INDEXED_DATA 0x10
  24. #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
  25. #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
  26. #define DENALI_MAP10 (2 << 26) /* high-level control plane */
  27. #define DENALI_MAP11 (3 << 26) /* direct controller access */
  28. /* MAP11 access cycle type */
  29. #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
  30. #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
  31. #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
  32. /* MAP10 commands */
  33. #define DENALI_ERASE 0x01
  34. #define DENALI_BANK(denali) ((denali)->active_bank << 24)
  35. #define DENALI_INVALID_BANK -1
  36. #define DENALI_NR_BANKS 4
  37. static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
  38. {
  39. return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
  40. }
  41. /*
  42. * Direct Addressing - the slave address forms the control information (command
  43. * type, bank, block, and page address). The slave data is the actual data to
  44. * be transferred. This mode requires 28 bits of address region allocated.
  45. */
  46. static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
  47. {
  48. return ioread32(denali->host + addr);
  49. }
  50. static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
  51. u32 data)
  52. {
  53. iowrite32(data, denali->host + addr);
  54. }
  55. /*
  56. * Indexed Addressing - address translation module intervenes in passing the
  57. * control information. This mode reduces the required address range. The
  58. * control information and transferred data are latched by the registers in
  59. * the translation module.
  60. */
  61. static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
  62. {
  63. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  64. return ioread32(denali->host + DENALI_INDEXED_DATA);
  65. }
  66. static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
  67. u32 data)
  68. {
  69. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  70. iowrite32(data, denali->host + DENALI_INDEXED_DATA);
  71. }
  72. /*
  73. * Use the configuration feature register to determine the maximum number of
  74. * banks that the hardware supports.
  75. */
  76. static void denali_detect_max_banks(struct denali_nand_info *denali)
  77. {
  78. uint32_t features = ioread32(denali->reg + FEATURES);
  79. denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
  80. /* the encoding changed from rev 5.0 to 5.1 */
  81. if (denali->revision < 0x0501)
  82. denali->max_banks <<= 1;
  83. }
  84. static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
  85. {
  86. int i;
  87. for (i = 0; i < DENALI_NR_BANKS; i++)
  88. iowrite32(U32_MAX, denali->reg + INTR_EN(i));
  89. iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
  90. }
  91. static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
  92. {
  93. int i;
  94. for (i = 0; i < DENALI_NR_BANKS; i++)
  95. iowrite32(0, denali->reg + INTR_EN(i));
  96. iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
  97. }
  98. static void denali_clear_irq(struct denali_nand_info *denali,
  99. int bank, uint32_t irq_status)
  100. {
  101. /* write one to clear bits */
  102. iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
  103. }
  104. static void denali_clear_irq_all(struct denali_nand_info *denali)
  105. {
  106. int i;
  107. for (i = 0; i < DENALI_NR_BANKS; i++)
  108. denali_clear_irq(denali, i, U32_MAX);
  109. }
  110. static void __denali_check_irq(struct denali_nand_info *denali)
  111. {
  112. uint32_t irq_status;
  113. int i;
  114. for (i = 0; i < DENALI_NR_BANKS; i++) {
  115. irq_status = ioread32(denali->reg + INTR_STATUS(i));
  116. denali_clear_irq(denali, i, irq_status);
  117. if (i != denali->active_bank)
  118. continue;
  119. denali->irq_status |= irq_status;
  120. }
  121. }
  122. static void denali_reset_irq(struct denali_nand_info *denali)
  123. {
  124. denali->irq_status = 0;
  125. denali->irq_mask = 0;
  126. }
  127. static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
  128. uint32_t irq_mask)
  129. {
  130. unsigned long time_left = 1000000;
  131. while (time_left) {
  132. __denali_check_irq(denali);
  133. if (irq_mask & denali->irq_status)
  134. return denali->irq_status;
  135. udelay(1);
  136. time_left--;
  137. }
  138. if (!time_left) {
  139. dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
  140. irq_mask);
  141. return 0;
  142. }
  143. return denali->irq_status;
  144. }
  145. static uint32_t denali_check_irq(struct denali_nand_info *denali)
  146. {
  147. __denali_check_irq(denali);
  148. return denali->irq_status;
  149. }
  150. static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  151. {
  152. struct denali_nand_info *denali = mtd_to_denali(mtd);
  153. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  154. int i;
  155. for (i = 0; i < len; i++)
  156. buf[i] = denali->host_read(denali, addr);
  157. }
  158. static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  159. {
  160. struct denali_nand_info *denali = mtd_to_denali(mtd);
  161. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  162. int i;
  163. for (i = 0; i < len; i++)
  164. denali->host_write(denali, addr, buf[i]);
  165. }
  166. static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  167. {
  168. struct denali_nand_info *denali = mtd_to_denali(mtd);
  169. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  170. uint16_t *buf16 = (uint16_t *)buf;
  171. int i;
  172. for (i = 0; i < len / 2; i++)
  173. buf16[i] = denali->host_read(denali, addr);
  174. }
  175. static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
  176. int len)
  177. {
  178. struct denali_nand_info *denali = mtd_to_denali(mtd);
  179. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  180. const uint16_t *buf16 = (const uint16_t *)buf;
  181. int i;
  182. for (i = 0; i < len / 2; i++)
  183. denali->host_write(denali, addr, buf16[i]);
  184. }
  185. static uint8_t denali_read_byte(struct mtd_info *mtd)
  186. {
  187. uint8_t byte;
  188. denali_read_buf(mtd, &byte, 1);
  189. return byte;
  190. }
  191. static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
  192. {
  193. denali_write_buf(mtd, &byte, 1);
  194. }
  195. static uint16_t denali_read_word(struct mtd_info *mtd)
  196. {
  197. uint16_t word;
  198. denali_read_buf16(mtd, (uint8_t *)&word, 2);
  199. return word;
  200. }
  201. static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
  202. {
  203. struct denali_nand_info *denali = mtd_to_denali(mtd);
  204. uint32_t type;
  205. if (ctrl & NAND_CLE)
  206. type = DENALI_MAP11_CMD;
  207. else if (ctrl & NAND_ALE)
  208. type = DENALI_MAP11_ADDR;
  209. else
  210. return;
  211. /*
  212. * Some commands are followed by chip->dev_ready or chip->waitfunc.
  213. * irq_status must be cleared here to catch the R/B# interrupt later.
  214. */
  215. if (ctrl & NAND_CTRL_CHANGE)
  216. denali_reset_irq(denali);
  217. denali->host_write(denali, DENALI_BANK(denali) | type, dat);
  218. }
  219. static int denali_dev_ready(struct mtd_info *mtd)
  220. {
  221. struct denali_nand_info *denali = mtd_to_denali(mtd);
  222. return !!(denali_check_irq(denali) & INTR__INT_ACT);
  223. }
  224. static int denali_check_erased_page(struct mtd_info *mtd,
  225. struct nand_chip *chip, uint8_t *buf,
  226. unsigned long uncor_ecc_flags,
  227. unsigned int max_bitflips)
  228. {
  229. uint8_t *ecc_code = chip->buffers->ecccode;
  230. int ecc_steps = chip->ecc.steps;
  231. int ecc_size = chip->ecc.size;
  232. int ecc_bytes = chip->ecc.bytes;
  233. int i, ret, stat;
  234. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  235. chip->ecc.total);
  236. if (ret)
  237. return ret;
  238. for (i = 0; i < ecc_steps; i++) {
  239. if (!(uncor_ecc_flags & BIT(i)))
  240. continue;
  241. stat = nand_check_erased_ecc_chunk(buf, ecc_size,
  242. ecc_code, ecc_bytes,
  243. NULL, 0,
  244. chip->ecc.strength);
  245. if (stat < 0) {
  246. mtd->ecc_stats.failed++;
  247. } else {
  248. mtd->ecc_stats.corrected += stat;
  249. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  250. }
  251. buf += ecc_size;
  252. ecc_code += ecc_bytes;
  253. }
  254. return max_bitflips;
  255. }
  256. static int denali_hw_ecc_fixup(struct mtd_info *mtd,
  257. struct denali_nand_info *denali,
  258. unsigned long *uncor_ecc_flags)
  259. {
  260. struct nand_chip *chip = mtd_to_nand(mtd);
  261. int bank = denali->active_bank;
  262. uint32_t ecc_cor;
  263. unsigned int max_bitflips;
  264. ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
  265. ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
  266. if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
  267. /*
  268. * This flag is set when uncorrectable error occurs at least in
  269. * one ECC sector. We can not know "how many sectors", or
  270. * "which sector(s)". We need erase-page check for all sectors.
  271. */
  272. *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
  273. return 0;
  274. }
  275. max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
  276. /*
  277. * The register holds the maximum of per-sector corrected bitflips.
  278. * This is suitable for the return value of the ->read_page() callback.
  279. * Unfortunately, we can not know the total number of corrected bits in
  280. * the page. Increase the stats by max_bitflips. (compromised solution)
  281. */
  282. mtd->ecc_stats.corrected += max_bitflips;
  283. return max_bitflips;
  284. }
  285. static int denali_sw_ecc_fixup(struct mtd_info *mtd,
  286. struct denali_nand_info *denali,
  287. unsigned long *uncor_ecc_flags, uint8_t *buf)
  288. {
  289. unsigned int ecc_size = denali->nand.ecc.size;
  290. unsigned int bitflips = 0;
  291. unsigned int max_bitflips = 0;
  292. uint32_t err_addr, err_cor_info;
  293. unsigned int err_byte, err_sector, err_device;
  294. uint8_t err_cor_value;
  295. unsigned int prev_sector = 0;
  296. uint32_t irq_status;
  297. denali_reset_irq(denali);
  298. do {
  299. err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
  300. err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
  301. err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
  302. err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
  303. err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
  304. err_cor_info);
  305. err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
  306. err_cor_info);
  307. /* reset the bitflip counter when crossing ECC sector */
  308. if (err_sector != prev_sector)
  309. bitflips = 0;
  310. if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
  311. /*
  312. * Check later if this is a real ECC error, or
  313. * an erased sector.
  314. */
  315. *uncor_ecc_flags |= BIT(err_sector);
  316. } else if (err_byte < ecc_size) {
  317. /*
  318. * If err_byte is larger than ecc_size, means error
  319. * happened in OOB, so we ignore it. It's no need for
  320. * us to correct it err_device is represented the NAND
  321. * error bits are happened in if there are more than
  322. * one NAND connected.
  323. */
  324. int offset;
  325. unsigned int flips_in_byte;
  326. offset = (err_sector * ecc_size + err_byte) *
  327. denali->devs_per_cs + err_device;
  328. /* correct the ECC error */
  329. flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
  330. buf[offset] ^= err_cor_value;
  331. mtd->ecc_stats.corrected += flips_in_byte;
  332. bitflips += flips_in_byte;
  333. max_bitflips = max(max_bitflips, bitflips);
  334. }
  335. prev_sector = err_sector;
  336. } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
  337. /*
  338. * Once handle all ECC errors, controller will trigger an
  339. * ECC_TRANSACTION_DONE interrupt.
  340. */
  341. irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
  342. if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
  343. return -EIO;
  344. return max_bitflips;
  345. }
  346. static void denali_setup_dma64(struct denali_nand_info *denali,
  347. dma_addr_t dma_addr, int page, int write)
  348. {
  349. uint32_t mode;
  350. const int page_count = 1;
  351. mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
  352. /* DMA is a three step process */
  353. /*
  354. * 1. setup transfer type, interrupt when complete,
  355. * burst len = 64 bytes, the number of pages
  356. */
  357. denali->host_write(denali, mode,
  358. 0x01002000 | (64 << 16) | (write << 8) | page_count);
  359. /* 2. set memory low address */
  360. denali->host_write(denali, mode, lower_32_bits(dma_addr));
  361. /* 3. set memory high address */
  362. denali->host_write(denali, mode, upper_32_bits(dma_addr));
  363. }
  364. static void denali_setup_dma32(struct denali_nand_info *denali,
  365. dma_addr_t dma_addr, int page, int write)
  366. {
  367. uint32_t mode;
  368. const int page_count = 1;
  369. mode = DENALI_MAP10 | DENALI_BANK(denali);
  370. /* DMA is a four step process */
  371. /* 1. setup transfer type and # of pages */
  372. denali->host_write(denali, mode | page,
  373. 0x2000 | (write << 8) | page_count);
  374. /* 2. set memory high address bits 23:8 */
  375. denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
  376. /* 3. set memory low address bits 23:8 */
  377. denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
  378. /* 4. interrupt when complete, burst len = 64 bytes */
  379. denali->host_write(denali, mode | 0x14000, 0x2400);
  380. }
  381. static int denali_pio_read(struct denali_nand_info *denali, void *buf,
  382. size_t size, int page, int raw)
  383. {
  384. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  385. uint32_t *buf32 = (uint32_t *)buf;
  386. uint32_t irq_status, ecc_err_mask;
  387. int i;
  388. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  389. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  390. else
  391. ecc_err_mask = INTR__ECC_ERR;
  392. denali_reset_irq(denali);
  393. for (i = 0; i < size / 4; i++)
  394. *buf32++ = denali->host_read(denali, addr);
  395. irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
  396. if (!(irq_status & INTR__PAGE_XFER_INC))
  397. return -EIO;
  398. if (irq_status & INTR__ERASED_PAGE)
  399. memset(buf, 0xff, size);
  400. return irq_status & ecc_err_mask ? -EBADMSG : 0;
  401. }
  402. static int denali_pio_write(struct denali_nand_info *denali,
  403. const void *buf, size_t size, int page, int raw)
  404. {
  405. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  406. const uint32_t *buf32 = (uint32_t *)buf;
  407. uint32_t irq_status;
  408. int i;
  409. denali_reset_irq(denali);
  410. for (i = 0; i < size / 4; i++)
  411. denali->host_write(denali, addr, *buf32++);
  412. irq_status = denali_wait_for_irq(denali,
  413. INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
  414. if (!(irq_status & INTR__PROGRAM_COMP))
  415. return -EIO;
  416. return 0;
  417. }
  418. static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
  419. size_t size, int page, int raw, int write)
  420. {
  421. if (write)
  422. return denali_pio_write(denali, buf, size, page, raw);
  423. else
  424. return denali_pio_read(denali, buf, size, page, raw);
  425. }
  426. static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
  427. size_t size, int page, int raw, int write)
  428. {
  429. dma_addr_t dma_addr;
  430. uint32_t irq_mask, irq_status, ecc_err_mask;
  431. enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  432. int ret = 0;
  433. dma_addr = dma_map_single(buf, size, dir);
  434. if (dma_mapping_error(denali->dev, dma_addr)) {
  435. dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
  436. return denali_pio_xfer(denali, buf, size, page, raw, write);
  437. }
  438. if (write) {
  439. /*
  440. * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
  441. * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
  442. * when the page program is completed.
  443. */
  444. irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
  445. ecc_err_mask = 0;
  446. } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
  447. irq_mask = INTR__DMA_CMD_COMP;
  448. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  449. } else {
  450. irq_mask = INTR__DMA_CMD_COMP;
  451. ecc_err_mask = INTR__ECC_ERR;
  452. }
  453. iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
  454. /*
  455. * The ->setup_dma() hook kicks DMA by using the data/command
  456. * interface, which belongs to a different AXI port from the
  457. * register interface. Read back the register to avoid a race.
  458. */
  459. ioread32(denali->reg + DMA_ENABLE);
  460. denali_reset_irq(denali);
  461. denali->setup_dma(denali, dma_addr, page, write);
  462. irq_status = denali_wait_for_irq(denali, irq_mask);
  463. if (!(irq_status & INTR__DMA_CMD_COMP))
  464. ret = -EIO;
  465. else if (irq_status & ecc_err_mask)
  466. ret = -EBADMSG;
  467. iowrite32(0, denali->reg + DMA_ENABLE);
  468. dma_unmap_single(dma_addr, size, dir);
  469. if (irq_status & INTR__ERASED_PAGE)
  470. memset(buf, 0xff, size);
  471. return ret;
  472. }
  473. static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
  474. size_t size, int page, int raw, int write)
  475. {
  476. iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
  477. iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
  478. denali->reg + TRANSFER_SPARE_REG);
  479. if (denali->dma_avail)
  480. return denali_dma_xfer(denali, buf, size, page, raw, write);
  481. else
  482. return denali_pio_xfer(denali, buf, size, page, raw, write);
  483. }
  484. static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
  485. int page, int write)
  486. {
  487. struct denali_nand_info *denali = mtd_to_denali(mtd);
  488. unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
  489. unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
  490. int writesize = mtd->writesize;
  491. int oobsize = mtd->oobsize;
  492. uint8_t *bufpoi = chip->oob_poi;
  493. int ecc_steps = chip->ecc.steps;
  494. int ecc_size = chip->ecc.size;
  495. int ecc_bytes = chip->ecc.bytes;
  496. int oob_skip = denali->oob_skip_bytes;
  497. size_t size = writesize + oobsize;
  498. int i, pos, len;
  499. /* BBM at the beginning of the OOB area */
  500. chip->cmdfunc(mtd, start_cmd, writesize, page);
  501. if (write)
  502. chip->write_buf(mtd, bufpoi, oob_skip);
  503. else
  504. chip->read_buf(mtd, bufpoi, oob_skip);
  505. bufpoi += oob_skip;
  506. /* OOB ECC */
  507. for (i = 0; i < ecc_steps; i++) {
  508. pos = ecc_size + i * (ecc_size + ecc_bytes);
  509. len = ecc_bytes;
  510. if (pos >= writesize)
  511. pos += oob_skip;
  512. else if (pos + len > writesize)
  513. len = writesize - pos;
  514. chip->cmdfunc(mtd, rnd_cmd, pos, -1);
  515. if (write)
  516. chip->write_buf(mtd, bufpoi, len);
  517. else
  518. chip->read_buf(mtd, bufpoi, len);
  519. bufpoi += len;
  520. if (len < ecc_bytes) {
  521. len = ecc_bytes - len;
  522. chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
  523. if (write)
  524. chip->write_buf(mtd, bufpoi, len);
  525. else
  526. chip->read_buf(mtd, bufpoi, len);
  527. bufpoi += len;
  528. }
  529. }
  530. /* OOB free */
  531. len = oobsize - (bufpoi - chip->oob_poi);
  532. chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
  533. if (write)
  534. chip->write_buf(mtd, bufpoi, len);
  535. else
  536. chip->read_buf(mtd, bufpoi, len);
  537. }
  538. static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  539. uint8_t *buf, int oob_required, int page)
  540. {
  541. struct denali_nand_info *denali = mtd_to_denali(mtd);
  542. int writesize = mtd->writesize;
  543. int oobsize = mtd->oobsize;
  544. int ecc_steps = chip->ecc.steps;
  545. int ecc_size = chip->ecc.size;
  546. int ecc_bytes = chip->ecc.bytes;
  547. void *tmp_buf = denali->buf;
  548. int oob_skip = denali->oob_skip_bytes;
  549. size_t size = writesize + oobsize;
  550. int ret, i, pos, len;
  551. ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
  552. if (ret)
  553. return ret;
  554. /* Arrange the buffer for syndrome payload/ecc layout */
  555. if (buf) {
  556. for (i = 0; i < ecc_steps; i++) {
  557. pos = i * (ecc_size + ecc_bytes);
  558. len = ecc_size;
  559. if (pos >= writesize)
  560. pos += oob_skip;
  561. else if (pos + len > writesize)
  562. len = writesize - pos;
  563. memcpy(buf, tmp_buf + pos, len);
  564. buf += len;
  565. if (len < ecc_size) {
  566. len = ecc_size - len;
  567. memcpy(buf, tmp_buf + writesize + oob_skip,
  568. len);
  569. buf += len;
  570. }
  571. }
  572. }
  573. if (oob_required) {
  574. uint8_t *oob = chip->oob_poi;
  575. /* BBM at the beginning of the OOB area */
  576. memcpy(oob, tmp_buf + writesize, oob_skip);
  577. oob += oob_skip;
  578. /* OOB ECC */
  579. for (i = 0; i < ecc_steps; i++) {
  580. pos = ecc_size + i * (ecc_size + ecc_bytes);
  581. len = ecc_bytes;
  582. if (pos >= writesize)
  583. pos += oob_skip;
  584. else if (pos + len > writesize)
  585. len = writesize - pos;
  586. memcpy(oob, tmp_buf + pos, len);
  587. oob += len;
  588. if (len < ecc_bytes) {
  589. len = ecc_bytes - len;
  590. memcpy(oob, tmp_buf + writesize + oob_skip,
  591. len);
  592. oob += len;
  593. }
  594. }
  595. /* OOB free */
  596. len = oobsize - (oob - chip->oob_poi);
  597. memcpy(oob, tmp_buf + size - len, len);
  598. }
  599. return 0;
  600. }
  601. static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  602. int page)
  603. {
  604. denali_oob_xfer(mtd, chip, page, 0);
  605. return 0;
  606. }
  607. static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  608. int page)
  609. {
  610. struct denali_nand_info *denali = mtd_to_denali(mtd);
  611. int status;
  612. denali_reset_irq(denali);
  613. denali_oob_xfer(mtd, chip, page, 1);
  614. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  615. status = chip->waitfunc(mtd, chip);
  616. return status & NAND_STATUS_FAIL ? -EIO : 0;
  617. }
  618. static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  619. uint8_t *buf, int oob_required, int page)
  620. {
  621. struct denali_nand_info *denali = mtd_to_denali(mtd);
  622. unsigned long uncor_ecc_flags = 0;
  623. int stat = 0;
  624. int ret;
  625. ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
  626. if (ret && ret != -EBADMSG)
  627. return ret;
  628. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  629. stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
  630. else if (ret == -EBADMSG)
  631. stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
  632. if (stat < 0)
  633. return stat;
  634. if (uncor_ecc_flags) {
  635. ret = denali_read_oob(mtd, chip, page);
  636. if (ret)
  637. return ret;
  638. stat = denali_check_erased_page(mtd, chip, buf,
  639. uncor_ecc_flags, stat);
  640. }
  641. return stat;
  642. }
  643. static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  644. const uint8_t *buf, int oob_required, int page)
  645. {
  646. struct denali_nand_info *denali = mtd_to_denali(mtd);
  647. int writesize = mtd->writesize;
  648. int oobsize = mtd->oobsize;
  649. int ecc_steps = chip->ecc.steps;
  650. int ecc_size = chip->ecc.size;
  651. int ecc_bytes = chip->ecc.bytes;
  652. void *tmp_buf = denali->buf;
  653. int oob_skip = denali->oob_skip_bytes;
  654. size_t size = writesize + oobsize;
  655. int i, pos, len;
  656. /*
  657. * Fill the buffer with 0xff first except the full page transfer.
  658. * This simplifies the logic.
  659. */
  660. if (!buf || !oob_required)
  661. memset(tmp_buf, 0xff, size);
  662. /* Arrange the buffer for syndrome payload/ecc layout */
  663. if (buf) {
  664. for (i = 0; i < ecc_steps; i++) {
  665. pos = i * (ecc_size + ecc_bytes);
  666. len = ecc_size;
  667. if (pos >= writesize)
  668. pos += oob_skip;
  669. else if (pos + len > writesize)
  670. len = writesize - pos;
  671. memcpy(tmp_buf + pos, buf, len);
  672. buf += len;
  673. if (len < ecc_size) {
  674. len = ecc_size - len;
  675. memcpy(tmp_buf + writesize + oob_skip, buf,
  676. len);
  677. buf += len;
  678. }
  679. }
  680. }
  681. if (oob_required) {
  682. const uint8_t *oob = chip->oob_poi;
  683. /* BBM at the beginning of the OOB area */
  684. memcpy(tmp_buf + writesize, oob, oob_skip);
  685. oob += oob_skip;
  686. /* OOB ECC */
  687. for (i = 0; i < ecc_steps; i++) {
  688. pos = ecc_size + i * (ecc_size + ecc_bytes);
  689. len = ecc_bytes;
  690. if (pos >= writesize)
  691. pos += oob_skip;
  692. else if (pos + len > writesize)
  693. len = writesize - pos;
  694. memcpy(tmp_buf + pos, oob, len);
  695. oob += len;
  696. if (len < ecc_bytes) {
  697. len = ecc_bytes - len;
  698. memcpy(tmp_buf + writesize + oob_skip, oob,
  699. len);
  700. oob += len;
  701. }
  702. }
  703. /* OOB free */
  704. len = oobsize - (oob - chip->oob_poi);
  705. memcpy(tmp_buf + size - len, oob, len);
  706. }
  707. return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
  708. }
  709. static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  710. const uint8_t *buf, int oob_required, int page)
  711. {
  712. struct denali_nand_info *denali = mtd_to_denali(mtd);
  713. return denali_data_xfer(denali, (void *)buf, mtd->writesize,
  714. page, 0, 1);
  715. }
  716. static void denali_select_chip(struct mtd_info *mtd, int chip)
  717. {
  718. struct denali_nand_info *denali = mtd_to_denali(mtd);
  719. denali->active_bank = chip;
  720. }
  721. static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
  722. {
  723. struct denali_nand_info *denali = mtd_to_denali(mtd);
  724. uint32_t irq_status;
  725. /* R/B# pin transitioned from low to high? */
  726. irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
  727. return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
  728. }
  729. static int denali_erase(struct mtd_info *mtd, int page)
  730. {
  731. struct denali_nand_info *denali = mtd_to_denali(mtd);
  732. uint32_t irq_status;
  733. denali_reset_irq(denali);
  734. denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
  735. DENALI_ERASE);
  736. /* wait for erase to complete or failure to occur */
  737. irq_status = denali_wait_for_irq(denali,
  738. INTR__ERASE_COMP | INTR__ERASE_FAIL);
  739. return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
  740. }
  741. static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
  742. const struct nand_data_interface *conf)
  743. {
  744. struct denali_nand_info *denali = mtd_to_denali(mtd);
  745. const struct nand_sdr_timings *timings;
  746. unsigned long t_x, mult_x;
  747. int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
  748. int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
  749. int addr_2_data_mask;
  750. uint32_t tmp;
  751. timings = nand_get_sdr_timings(conf);
  752. if (IS_ERR(timings))
  753. return PTR_ERR(timings);
  754. /* clk_x period in picoseconds */
  755. t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
  756. if (!t_x)
  757. return -EINVAL;
  758. /*
  759. * The bus interface clock, clk_x, is phase aligned with the core clock.
  760. * The clk_x is an integral multiple N of the core clk. The value N is
  761. * configured at IP delivery time, and its available value is 4, 5, 6.
  762. */
  763. mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
  764. if (mult_x < 4 || mult_x > 6)
  765. return -EINVAL;
  766. if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
  767. return 0;
  768. /* tREA -> ACC_CLKS */
  769. acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
  770. acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
  771. tmp = ioread32(denali->reg + ACC_CLKS);
  772. tmp &= ~ACC_CLKS__VALUE;
  773. tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
  774. iowrite32(tmp, denali->reg + ACC_CLKS);
  775. /* tRWH -> RE_2_WE */
  776. re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
  777. re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
  778. tmp = ioread32(denali->reg + RE_2_WE);
  779. tmp &= ~RE_2_WE__VALUE;
  780. tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
  781. iowrite32(tmp, denali->reg + RE_2_WE);
  782. /* tRHZ -> RE_2_RE */
  783. re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
  784. re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
  785. tmp = ioread32(denali->reg + RE_2_RE);
  786. tmp &= ~RE_2_RE__VALUE;
  787. tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
  788. iowrite32(tmp, denali->reg + RE_2_RE);
  789. /*
  790. * tCCS, tWHR -> WE_2_RE
  791. *
  792. * With WE_2_RE properly set, the Denali controller automatically takes
  793. * care of the delay; the driver need not set NAND_WAIT_TCCS.
  794. */
  795. we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
  796. we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
  797. tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
  798. tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
  799. tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
  800. iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
  801. /* tADL -> ADDR_2_DATA */
  802. /* for older versions, ADDR_2_DATA is only 6 bit wide */
  803. addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  804. if (denali->revision < 0x0501)
  805. addr_2_data_mask >>= 1;
  806. addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
  807. addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
  808. tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
  809. tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  810. tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
  811. iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
  812. /* tREH, tWH -> RDWR_EN_HI_CNT */
  813. rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
  814. t_x);
  815. rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
  816. tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
  817. tmp &= ~RDWR_EN_HI_CNT__VALUE;
  818. tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
  819. iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
  820. /* tRP, tWP -> RDWR_EN_LO_CNT */
  821. rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
  822. rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
  823. t_x);
  824. rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
  825. rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
  826. rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
  827. tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
  828. tmp &= ~RDWR_EN_LO_CNT__VALUE;
  829. tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
  830. iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
  831. /* tCS, tCEA -> CS_SETUP_CNT */
  832. cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
  833. (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
  834. 0);
  835. cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
  836. tmp = ioread32(denali->reg + CS_SETUP_CNT);
  837. tmp &= ~CS_SETUP_CNT__VALUE;
  838. tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
  839. iowrite32(tmp, denali->reg + CS_SETUP_CNT);
  840. return 0;
  841. }
  842. static void denali_reset_banks(struct denali_nand_info *denali)
  843. {
  844. u32 irq_status;
  845. int i;
  846. for (i = 0; i < denali->max_banks; i++) {
  847. denali->active_bank = i;
  848. denali_reset_irq(denali);
  849. iowrite32(DEVICE_RESET__BANK(i),
  850. denali->reg + DEVICE_RESET);
  851. irq_status = denali_wait_for_irq(denali,
  852. INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
  853. if (!(irq_status & INTR__INT_ACT))
  854. break;
  855. }
  856. dev_dbg(denali->dev, "%d chips connected\n", i);
  857. denali->max_banks = i;
  858. }
  859. static void denali_hw_init(struct denali_nand_info *denali)
  860. {
  861. /*
  862. * The REVISION register may not be reliable. Platforms are allowed to
  863. * override it.
  864. */
  865. if (!denali->revision)
  866. denali->revision = swab16(ioread32(denali->reg + REVISION));
  867. /*
  868. * Set how many bytes should be skipped before writing data in OOB.
  869. * If a platform requests a non-zero value, set it to the register.
  870. * Otherwise, read the value out, expecting it has already been set up
  871. * by firmware.
  872. */
  873. if (denali->oob_skip_bytes)
  874. iowrite32(denali->oob_skip_bytes,
  875. denali->reg + SPARE_AREA_SKIP_BYTES);
  876. else
  877. denali->oob_skip_bytes = ioread32(denali->reg +
  878. SPARE_AREA_SKIP_BYTES);
  879. denali_detect_max_banks(denali);
  880. iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
  881. iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
  882. iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
  883. }
  884. int denali_calc_ecc_bytes(int step_size, int strength)
  885. {
  886. /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
  887. return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
  888. }
  889. EXPORT_SYMBOL(denali_calc_ecc_bytes);
  890. static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
  891. struct denali_nand_info *denali)
  892. {
  893. int oobavail = mtd->oobsize - denali->oob_skip_bytes;
  894. int ret;
  895. /*
  896. * If .size and .strength are already set (usually by DT),
  897. * check if they are supported by this controller.
  898. */
  899. if (chip->ecc.size && chip->ecc.strength)
  900. return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
  901. /*
  902. * We want .size and .strength closest to the chip's requirement
  903. * unless NAND_ECC_MAXIMIZE is requested.
  904. */
  905. if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
  906. ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
  907. if (!ret)
  908. return 0;
  909. }
  910. /* Max ECC strength is the last thing we can do */
  911. return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
  912. }
  913. static struct nand_ecclayout nand_oob;
  914. static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
  915. struct mtd_oob_region *oobregion)
  916. {
  917. struct denali_nand_info *denali = mtd_to_denali(mtd);
  918. struct nand_chip *chip = mtd_to_nand(mtd);
  919. if (section)
  920. return -ERANGE;
  921. oobregion->offset = denali->oob_skip_bytes;
  922. oobregion->length = chip->ecc.total;
  923. return 0;
  924. }
  925. static int denali_ooblayout_free(struct mtd_info *mtd, int section,
  926. struct mtd_oob_region *oobregion)
  927. {
  928. struct denali_nand_info *denali = mtd_to_denali(mtd);
  929. struct nand_chip *chip = mtd_to_nand(mtd);
  930. if (section)
  931. return -ERANGE;
  932. oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
  933. oobregion->length = mtd->oobsize - oobregion->offset;
  934. return 0;
  935. }
  936. static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
  937. .ecc = denali_ooblayout_ecc,
  938. .rfree = denali_ooblayout_free,
  939. };
  940. static int denali_multidev_fixup(struct denali_nand_info *denali)
  941. {
  942. struct nand_chip *chip = &denali->nand;
  943. struct mtd_info *mtd = nand_to_mtd(chip);
  944. /*
  945. * Support for multi device:
  946. * When the IP configuration is x16 capable and two x8 chips are
  947. * connected in parallel, DEVICES_CONNECTED should be set to 2.
  948. * In this case, the core framework knows nothing about this fact,
  949. * so we should tell it the _logical_ pagesize and anything necessary.
  950. */
  951. denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
  952. /*
  953. * On some SoCs, DEVICES_CONNECTED is not auto-detected.
  954. * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
  955. */
  956. if (denali->devs_per_cs == 0) {
  957. denali->devs_per_cs = 1;
  958. iowrite32(1, denali->reg + DEVICES_CONNECTED);
  959. }
  960. if (denali->devs_per_cs == 1)
  961. return 0;
  962. if (denali->devs_per_cs != 2) {
  963. dev_err(denali->dev, "unsupported number of devices %d\n",
  964. denali->devs_per_cs);
  965. return -EINVAL;
  966. }
  967. /* 2 chips in parallel */
  968. mtd->size <<= 1;
  969. mtd->erasesize <<= 1;
  970. mtd->writesize <<= 1;
  971. mtd->oobsize <<= 1;
  972. chip->chipsize <<= 1;
  973. chip->page_shift += 1;
  974. chip->phys_erase_shift += 1;
  975. chip->bbt_erase_shift += 1;
  976. chip->chip_shift += 1;
  977. chip->pagemask <<= 1;
  978. chip->ecc.size <<= 1;
  979. chip->ecc.bytes <<= 1;
  980. chip->ecc.strength <<= 1;
  981. denali->oob_skip_bytes <<= 1;
  982. return 0;
  983. }
  984. int denali_init(struct denali_nand_info *denali)
  985. {
  986. struct nand_chip *chip = &denali->nand;
  987. struct mtd_info *mtd = nand_to_mtd(chip);
  988. u32 features = ioread32(denali->reg + FEATURES);
  989. int ret;
  990. denali_hw_init(denali);
  991. denali_clear_irq_all(denali);
  992. denali_reset_banks(denali);
  993. denali->active_bank = DENALI_INVALID_BANK;
  994. chip->flash_node = dev_of_offset(denali->dev);
  995. /* Fallback to the default name if DT did not give "label" property */
  996. if (!mtd->name)
  997. mtd->name = "denali-nand";
  998. chip->select_chip = denali_select_chip;
  999. chip->read_byte = denali_read_byte;
  1000. chip->write_byte = denali_write_byte;
  1001. chip->read_word = denali_read_word;
  1002. chip->cmd_ctrl = denali_cmd_ctrl;
  1003. chip->dev_ready = denali_dev_ready;
  1004. chip->waitfunc = denali_waitfunc;
  1005. if (features & FEATURES__INDEX_ADDR) {
  1006. denali->host_read = denali_indexed_read;
  1007. denali->host_write = denali_indexed_write;
  1008. } else {
  1009. denali->host_read = denali_direct_read;
  1010. denali->host_write = denali_direct_write;
  1011. }
  1012. /* clk rate info is needed for setup_data_interface */
  1013. if (denali->clk_x_rate)
  1014. chip->setup_data_interface = denali_setup_data_interface;
  1015. ret = nand_scan_ident(mtd, denali->max_banks, NULL);
  1016. if (ret)
  1017. return ret;
  1018. if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
  1019. denali->dma_avail = 1;
  1020. if (denali->dma_avail) {
  1021. chip->buf_align = ARCH_DMA_MINALIGN;
  1022. if (denali->caps & DENALI_CAP_DMA_64BIT)
  1023. denali->setup_dma = denali_setup_dma64;
  1024. else
  1025. denali->setup_dma = denali_setup_dma32;
  1026. } else {
  1027. chip->buf_align = 4;
  1028. }
  1029. chip->options |= NAND_USE_BOUNCE_BUFFER;
  1030. chip->bbt_options |= NAND_BBT_USE_FLASH;
  1031. chip->bbt_options |= NAND_BBT_NO_OOB;
  1032. denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
  1033. /* no subpage writes on denali */
  1034. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1035. ret = denali_ecc_setup(mtd, chip, denali);
  1036. if (ret) {
  1037. dev_err(denali->dev, "Failed to setup ECC settings.\n");
  1038. return ret;
  1039. }
  1040. dev_dbg(denali->dev,
  1041. "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
  1042. chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
  1043. iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
  1044. FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
  1045. denali->reg + ECC_CORRECTION);
  1046. iowrite32(mtd->erasesize / mtd->writesize,
  1047. denali->reg + PAGES_PER_BLOCK);
  1048. iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
  1049. denali->reg + DEVICE_WIDTH);
  1050. iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
  1051. denali->reg + TWO_ROW_ADDR_CYCLES);
  1052. iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
  1053. iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
  1054. iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
  1055. iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
  1056. /* chip->ecc.steps is set by nand_scan_tail(); not available here */
  1057. iowrite32(mtd->writesize / chip->ecc.size,
  1058. denali->reg + CFG_NUM_DATA_BLOCKS);
  1059. mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
  1060. nand_oob.eccbytes = denali->nand.ecc.bytes;
  1061. denali->nand.ecc.layout = &nand_oob;
  1062. if (chip->options & NAND_BUSWIDTH_16) {
  1063. chip->read_buf = denali_read_buf16;
  1064. chip->write_buf = denali_write_buf16;
  1065. } else {
  1066. chip->read_buf = denali_read_buf;
  1067. chip->write_buf = denali_write_buf;
  1068. }
  1069. chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
  1070. chip->ecc.read_page = denali_read_page;
  1071. chip->ecc.read_page_raw = denali_read_page_raw;
  1072. chip->ecc.write_page = denali_write_page;
  1073. chip->ecc.write_page_raw = denali_write_page_raw;
  1074. chip->ecc.read_oob = denali_read_oob;
  1075. chip->ecc.write_oob = denali_write_oob;
  1076. chip->erase = denali_erase;
  1077. ret = denali_multidev_fixup(denali);
  1078. if (ret)
  1079. return ret;
  1080. /*
  1081. * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
  1082. * use devm_kmalloc() because the memory allocated by devm_ does not
  1083. * guarantee DMA-safe alignment.
  1084. */
  1085. denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
  1086. if (!denali->buf)
  1087. return -ENOMEM;
  1088. ret = nand_scan_tail(mtd);
  1089. if (ret)
  1090. goto free_buf;
  1091. ret = nand_register(0, mtd);
  1092. if (ret) {
  1093. dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
  1094. goto free_buf;
  1095. }
  1096. return 0;
  1097. free_buf:
  1098. kfree(denali->buf);
  1099. return ret;
  1100. }