tmio-common.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <fdtdec.h>
  10. #include <mmc.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/pinctrl.h>
  14. #include <linux/compat.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/io.h>
  17. #include <linux/sizes.h>
  18. #include <power/regulator.h>
  19. #include <asm/unaligned.h>
  20. #include "tmio-common.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
  23. {
  24. return readq(priv->regbase + (reg << 1));
  25. }
  26. static void tmio_sd_writeq(struct tmio_sd_priv *priv,
  27. u64 val, unsigned int reg)
  28. {
  29. writeq(val, priv->regbase + (reg << 1));
  30. }
  31. static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
  32. {
  33. return readw(priv->regbase + (reg >> 1));
  34. }
  35. static void tmio_sd_writew(struct tmio_sd_priv *priv,
  36. u16 val, unsigned int reg)
  37. {
  38. writew(val, priv->regbase + (reg >> 1));
  39. }
  40. u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
  41. {
  42. u32 val;
  43. if (priv->caps & TMIO_SD_CAP_64BIT)
  44. return readl(priv->regbase + (reg << 1));
  45. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  46. val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  47. if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
  48. (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
  49. val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  50. }
  51. return val;
  52. } else
  53. return readl(priv->regbase + reg);
  54. }
  55. void tmio_sd_writel(struct tmio_sd_priv *priv,
  56. u32 val, unsigned int reg)
  57. {
  58. if (priv->caps & TMIO_SD_CAP_64BIT)
  59. writel(val, priv->regbase + (reg << 1));
  60. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  61. writew(val & 0xffff, priv->regbase + (reg >> 1));
  62. if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
  63. reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
  64. reg == TMIO_SD_ARG)
  65. writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  66. } else
  67. writel(val, priv->regbase + reg);
  68. }
  69. static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
  70. {
  71. struct tmio_sd_priv *priv = dev_get_priv(dev);
  72. u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
  73. if (info2 & TMIO_SD_INFO2_ERR_RTO) {
  74. /*
  75. * TIMEOUT must be returned for unsupported command. Do not
  76. * display error log since this might be a part of sequence to
  77. * distinguish between SD and MMC.
  78. */
  79. return -ETIMEDOUT;
  80. }
  81. if (info2 & TMIO_SD_INFO2_ERR_TO) {
  82. dev_err(dev, "timeout error\n");
  83. return -ETIMEDOUT;
  84. }
  85. if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
  86. TMIO_SD_INFO2_ERR_IDX)) {
  87. if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
  88. (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  89. dev_err(dev, "communication out of sync\n");
  90. return -EILSEQ;
  91. }
  92. if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
  93. TMIO_SD_INFO2_ERR_ILW)) {
  94. dev_err(dev, "illegal access\n");
  95. return -EIO;
  96. }
  97. return 0;
  98. }
  99. static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
  100. unsigned int reg, u32 flag)
  101. {
  102. struct tmio_sd_priv *priv = dev_get_priv(dev);
  103. long wait = 1000000;
  104. int ret;
  105. while (!(tmio_sd_readl(priv, reg) & flag)) {
  106. if (wait-- < 0) {
  107. dev_err(dev, "timeout\n");
  108. return -ETIMEDOUT;
  109. }
  110. ret = tmio_sd_check_error(dev, cmd);
  111. if (ret)
  112. return ret;
  113. udelay(1);
  114. }
  115. return 0;
  116. }
  117. #define tmio_pio_read_fifo(__width, __suffix) \
  118. static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
  119. char *pbuf, uint blksz) \
  120. { \
  121. u##__width *buf = (u##__width *)pbuf; \
  122. int i; \
  123. \
  124. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  125. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  126. *buf++ = tmio_sd_read##__suffix(priv, \
  127. TMIO_SD_BUF); \
  128. } \
  129. } else { \
  130. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  131. u##__width data; \
  132. data = tmio_sd_read##__suffix(priv, \
  133. TMIO_SD_BUF); \
  134. put_unaligned(data, buf++); \
  135. } \
  136. } \
  137. }
  138. tmio_pio_read_fifo(64, q)
  139. tmio_pio_read_fifo(32, l)
  140. tmio_pio_read_fifo(16, w)
  141. static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  142. char *pbuf, uint blocksize)
  143. {
  144. struct tmio_sd_priv *priv = dev_get_priv(dev);
  145. int ret;
  146. /* wait until the buffer is filled with data */
  147. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  148. TMIO_SD_INFO2_BRE);
  149. if (ret)
  150. return ret;
  151. /*
  152. * Clear the status flag _before_ read the buffer out because
  153. * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
  154. */
  155. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  156. if (priv->caps & TMIO_SD_CAP_64BIT)
  157. tmio_pio_read_fifo_64(priv, pbuf, blocksize);
  158. else if (priv->caps & TMIO_SD_CAP_16BIT)
  159. tmio_pio_read_fifo_16(priv, pbuf, blocksize);
  160. else
  161. tmio_pio_read_fifo_32(priv, pbuf, blocksize);
  162. return 0;
  163. }
  164. #define tmio_pio_write_fifo(__width, __suffix) \
  165. static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
  166. const char *pbuf, uint blksz)\
  167. { \
  168. const u##__width *buf = (const u##__width *)pbuf; \
  169. int i; \
  170. \
  171. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  172. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  173. tmio_sd_write##__suffix(priv, *buf++, \
  174. TMIO_SD_BUF); \
  175. } \
  176. } else { \
  177. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  178. u##__width data = get_unaligned(buf++); \
  179. tmio_sd_write##__suffix(priv, data, \
  180. TMIO_SD_BUF); \
  181. } \
  182. } \
  183. }
  184. tmio_pio_write_fifo(64, q)
  185. tmio_pio_write_fifo(32, l)
  186. tmio_pio_write_fifo(16, w)
  187. static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  188. const char *pbuf, uint blocksize)
  189. {
  190. struct tmio_sd_priv *priv = dev_get_priv(dev);
  191. int ret;
  192. /* wait until the buffer becomes empty */
  193. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  194. TMIO_SD_INFO2_BWE);
  195. if (ret)
  196. return ret;
  197. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  198. if (priv->caps & TMIO_SD_CAP_64BIT)
  199. tmio_pio_write_fifo_64(priv, pbuf, blocksize);
  200. else if (priv->caps & TMIO_SD_CAP_16BIT)
  201. tmio_pio_write_fifo_16(priv, pbuf, blocksize);
  202. else
  203. tmio_pio_write_fifo_32(priv, pbuf, blocksize);
  204. return 0;
  205. }
  206. static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
  207. struct mmc_data *data)
  208. {
  209. const char *src = data->src;
  210. char *dest = data->dest;
  211. int i, ret;
  212. for (i = 0; i < data->blocks; i++) {
  213. if (data->flags & MMC_DATA_READ)
  214. ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
  215. data->blocksize);
  216. else
  217. ret = tmio_sd_pio_write_one_block(dev, cmd, src,
  218. data->blocksize);
  219. if (ret)
  220. return ret;
  221. if (data->flags & MMC_DATA_READ)
  222. dest += data->blocksize;
  223. else
  224. src += data->blocksize;
  225. }
  226. return 0;
  227. }
  228. static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
  229. dma_addr_t dma_addr)
  230. {
  231. u32 tmp;
  232. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
  233. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
  234. /* enable DMA */
  235. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  236. tmp |= TMIO_SD_EXTMODE_DMA_EN;
  237. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  238. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
  239. /* suppress the warning "right shift count >= width of type" */
  240. dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
  241. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
  242. tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
  243. }
  244. static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
  245. unsigned int blocks)
  246. {
  247. struct tmio_sd_priv *priv = dev_get_priv(dev);
  248. long wait = 1000000 + 10 * blocks;
  249. while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
  250. if (wait-- < 0) {
  251. dev_err(dev, "timeout during DMA\n");
  252. return -ETIMEDOUT;
  253. }
  254. udelay(10);
  255. }
  256. if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
  257. dev_err(dev, "error during DMA\n");
  258. return -EIO;
  259. }
  260. return 0;
  261. }
  262. static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
  263. {
  264. struct tmio_sd_priv *priv = dev_get_priv(dev);
  265. size_t len = data->blocks * data->blocksize;
  266. void *buf;
  267. enum dma_data_direction dir;
  268. dma_addr_t dma_addr;
  269. u32 poll_flag, tmp;
  270. int ret;
  271. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  272. if (data->flags & MMC_DATA_READ) {
  273. buf = data->dest;
  274. dir = DMA_FROM_DEVICE;
  275. /*
  276. * The DMA READ completion flag position differs on Socionext
  277. * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
  278. * bit 17 is a hardware bug and forbidden. It is either bit 17
  279. * or bit 20 on Renesas SoCs, depending on SoC.
  280. */
  281. poll_flag = priv->read_poll_flag;
  282. tmp |= TMIO_SD_DMA_MODE_DIR_RD;
  283. } else {
  284. buf = (void *)data->src;
  285. dir = DMA_TO_DEVICE;
  286. poll_flag = TMIO_SD_DMA_INFO1_END_WR;
  287. tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
  288. }
  289. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  290. dma_addr = dma_map_single(buf, len, dir);
  291. tmio_sd_dma_start(priv, dma_addr);
  292. ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
  293. if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
  294. udelay(1);
  295. dma_unmap_single(dma_addr, len, dir);
  296. return ret;
  297. }
  298. /* check if the address is DMA'able */
  299. static bool tmio_sd_addr_is_dmaable(const char *src)
  300. {
  301. uintptr_t addr = (uintptr_t)src;
  302. if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
  303. return false;
  304. #if defined(CONFIG_RCAR_GEN3)
  305. /* Gen3 DMA has 32bit limit */
  306. if (addr >> 32)
  307. return false;
  308. #endif
  309. #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
  310. defined(CONFIG_SPL_BUILD)
  311. /*
  312. * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
  313. * of L2, which is unreachable from the DMA engine.
  314. */
  315. if (addr < CONFIG_SPL_STACK)
  316. return false;
  317. #endif
  318. return true;
  319. }
  320. int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  321. struct mmc_data *data)
  322. {
  323. struct tmio_sd_priv *priv = dev_get_priv(dev);
  324. int ret;
  325. u32 tmp;
  326. if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
  327. dev_err(dev, "command busy\n");
  328. return -EBUSY;
  329. }
  330. /* clear all status flags */
  331. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  332. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  333. /* disable DMA once */
  334. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  335. tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
  336. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  337. tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
  338. tmp = cmd->cmdidx;
  339. if (data) {
  340. tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
  341. tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
  342. /* Do not send CMD12 automatically */
  343. tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
  344. if (data->blocks > 1)
  345. tmp |= TMIO_SD_CMD_MULTI;
  346. if (data->flags & MMC_DATA_READ)
  347. tmp |= TMIO_SD_CMD_RD;
  348. }
  349. /*
  350. * Do not use the response type auto-detection on this hardware.
  351. * CMD8, for example, has different response types on SD and eMMC,
  352. * while this controller always assumes the response type for SD.
  353. * Set the response type manually.
  354. */
  355. switch (cmd->resp_type) {
  356. case MMC_RSP_NONE:
  357. tmp |= TMIO_SD_CMD_RSP_NONE;
  358. break;
  359. case MMC_RSP_R1:
  360. tmp |= TMIO_SD_CMD_RSP_R1;
  361. break;
  362. case MMC_RSP_R1b:
  363. tmp |= TMIO_SD_CMD_RSP_R1B;
  364. break;
  365. case MMC_RSP_R2:
  366. tmp |= TMIO_SD_CMD_RSP_R2;
  367. break;
  368. case MMC_RSP_R3:
  369. tmp |= TMIO_SD_CMD_RSP_R3;
  370. break;
  371. default:
  372. dev_err(dev, "unknown response type\n");
  373. return -EINVAL;
  374. }
  375. dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
  376. cmd->cmdidx, tmp, cmd->cmdarg);
  377. tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
  378. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  379. TMIO_SD_INFO1_RSP);
  380. if (ret)
  381. return ret;
  382. if (cmd->resp_type & MMC_RSP_136) {
  383. u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
  384. u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
  385. u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
  386. u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
  387. cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
  388. ((rsp_103_72 & 0xff000000) >> 24);
  389. cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
  390. ((rsp_71_40 & 0xff000000) >> 24);
  391. cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
  392. ((rsp_39_8 & 0xff000000) >> 24);
  393. cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
  394. } else {
  395. /* bit 39-8 */
  396. cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
  397. }
  398. if (data) {
  399. /* use DMA if the HW supports it and the buffer is aligned */
  400. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
  401. tmio_sd_addr_is_dmaable(data->src))
  402. ret = tmio_sd_dma_xfer(dev, data);
  403. else
  404. ret = tmio_sd_pio_xfer(dev, cmd, data);
  405. if (ret)
  406. return ret;
  407. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  408. TMIO_SD_INFO1_CMP);
  409. if (ret)
  410. return ret;
  411. }
  412. return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  413. TMIO_SD_INFO2_SCLKDIVEN);
  414. }
  415. static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
  416. struct mmc *mmc)
  417. {
  418. u32 val, tmp;
  419. switch (mmc->bus_width) {
  420. case 0:
  421. case 1:
  422. val = TMIO_SD_OPTION_WIDTH_1;
  423. break;
  424. case 4:
  425. val = TMIO_SD_OPTION_WIDTH_4;
  426. break;
  427. case 8:
  428. val = TMIO_SD_OPTION_WIDTH_8;
  429. break;
  430. default:
  431. return -EINVAL;
  432. }
  433. tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
  434. tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
  435. tmp |= val;
  436. tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
  437. return 0;
  438. }
  439. static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
  440. struct mmc *mmc)
  441. {
  442. u32 tmp;
  443. tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
  444. if (mmc->ddr_mode)
  445. tmp |= TMIO_SD_IF_MODE_DDR;
  446. else
  447. tmp &= ~TMIO_SD_IF_MODE_DDR;
  448. tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
  449. }
  450. static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
  451. {
  452. return priv->clk_get_rate(priv);
  453. }
  454. static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
  455. {
  456. unsigned int divisor;
  457. u32 tmp, val = 0;
  458. ulong mclk;
  459. if (mmc->clock) {
  460. mclk = tmio_sd_clk_get_rate(priv);
  461. divisor = DIV_ROUND_UP(mclk, mmc->clock);
  462. /* Do not set divider to 0xff in DDR mode */
  463. if (mmc->ddr_mode && (divisor == 1))
  464. divisor = 2;
  465. if (divisor <= 1)
  466. val = (priv->caps & TMIO_SD_CAP_RCAR) ?
  467. TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
  468. else if (divisor <= 2)
  469. val = TMIO_SD_CLKCTL_DIV2;
  470. else if (divisor <= 4)
  471. val = TMIO_SD_CLKCTL_DIV4;
  472. else if (divisor <= 8)
  473. val = TMIO_SD_CLKCTL_DIV8;
  474. else if (divisor <= 16)
  475. val = TMIO_SD_CLKCTL_DIV16;
  476. else if (divisor <= 32)
  477. val = TMIO_SD_CLKCTL_DIV32;
  478. else if (divisor <= 64)
  479. val = TMIO_SD_CLKCTL_DIV64;
  480. else if (divisor <= 128)
  481. val = TMIO_SD_CLKCTL_DIV128;
  482. else if (divisor <= 256)
  483. val = TMIO_SD_CLKCTL_DIV256;
  484. else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
  485. val = TMIO_SD_CLKCTL_DIV512;
  486. else
  487. val = TMIO_SD_CLKCTL_DIV1024;
  488. }
  489. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  490. if (mmc->clock &&
  491. !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
  492. ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
  493. /*
  494. * Stop the clock before changing its rate
  495. * to avoid a glitch signal
  496. */
  497. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  498. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  499. /* Change the clock rate. */
  500. tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
  501. tmp |= val;
  502. }
  503. /* Enable or Disable the clock */
  504. if (mmc->clk_disable) {
  505. tmp |= TMIO_SD_CLKCTL_OFFEN;
  506. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  507. } else {
  508. tmp &= ~TMIO_SD_CLKCTL_OFFEN;
  509. tmp |= TMIO_SD_CLKCTL_SCLKEN;
  510. }
  511. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  512. udelay(1000);
  513. }
  514. static void tmio_sd_set_pins(struct udevice *dev)
  515. {
  516. __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
  517. #ifdef CONFIG_DM_REGULATOR
  518. struct tmio_sd_priv *priv = dev_get_priv(dev);
  519. if (priv->vqmmc_dev) {
  520. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  521. regulator_set_value(priv->vqmmc_dev, 1800000);
  522. else
  523. regulator_set_value(priv->vqmmc_dev, 3300000);
  524. regulator_set_enable(priv->vqmmc_dev, true);
  525. }
  526. #endif
  527. #ifdef CONFIG_PINCTRL
  528. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  529. pinctrl_select_state(dev, "state_uhs");
  530. else
  531. pinctrl_select_state(dev, "default");
  532. #endif
  533. }
  534. int tmio_sd_set_ios(struct udevice *dev)
  535. {
  536. struct tmio_sd_priv *priv = dev_get_priv(dev);
  537. struct mmc *mmc = mmc_get_mmc_dev(dev);
  538. int ret;
  539. dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
  540. mmc->clock, mmc->ddr_mode, mmc->bus_width);
  541. tmio_sd_set_clk_rate(priv, mmc);
  542. ret = tmio_sd_set_bus_width(priv, mmc);
  543. if (ret)
  544. return ret;
  545. tmio_sd_set_ddr_mode(priv, mmc);
  546. tmio_sd_set_pins(dev);
  547. return 0;
  548. }
  549. int tmio_sd_get_cd(struct udevice *dev)
  550. {
  551. struct tmio_sd_priv *priv = dev_get_priv(dev);
  552. if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
  553. return 1;
  554. return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
  555. TMIO_SD_INFO1_CD);
  556. }
  557. static void tmio_sd_host_init(struct tmio_sd_priv *priv)
  558. {
  559. u32 tmp;
  560. /* soft reset of the host */
  561. tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
  562. tmp &= ~TMIO_SD_SOFT_RST_RSTX;
  563. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  564. tmp |= TMIO_SD_SOFT_RST_RSTX;
  565. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  566. /* FIXME: implement eMMC hw_reset */
  567. tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
  568. /*
  569. * Connected to 32bit AXI.
  570. * This register dropped backward compatibility at version 0x10.
  571. * Write an appropriate value depending on the IP version.
  572. */
  573. if (priv->version >= 0x10) {
  574. if (priv->caps & TMIO_SD_CAP_64BIT)
  575. tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
  576. else
  577. tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
  578. } else {
  579. tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
  580. }
  581. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
  582. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  583. tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
  584. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  585. }
  586. }
  587. int tmio_sd_bind(struct udevice *dev)
  588. {
  589. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  590. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  591. }
  592. int tmio_sd_probe(struct udevice *dev, u32 quirks)
  593. {
  594. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  595. struct tmio_sd_priv *priv = dev_get_priv(dev);
  596. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  597. fdt_addr_t base;
  598. ulong mclk;
  599. int ret;
  600. base = devfdt_get_addr(dev);
  601. if (base == FDT_ADDR_T_NONE)
  602. return -EINVAL;
  603. priv->regbase = devm_ioremap(dev, base, SZ_2K);
  604. if (!priv->regbase)
  605. return -ENOMEM;
  606. #ifdef CONFIG_DM_REGULATOR
  607. device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
  608. if (priv->vqmmc_dev)
  609. regulator_set_value(priv->vqmmc_dev, 3300000);
  610. #endif
  611. ret = mmc_of_parse(dev, &plat->cfg);
  612. if (ret < 0) {
  613. dev_err(dev, "failed to parse host caps\n");
  614. return ret;
  615. }
  616. plat->cfg.name = dev->name;
  617. plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  618. if (quirks)
  619. priv->caps = quirks;
  620. priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
  621. TMIO_SD_VERSION_IP;
  622. dev_dbg(dev, "version %x\n", priv->version);
  623. if (priv->version >= 0x10) {
  624. priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
  625. priv->caps |= TMIO_SD_CAP_DIV1024;
  626. }
  627. if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
  628. NULL))
  629. priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
  630. tmio_sd_host_init(priv);
  631. mclk = tmio_sd_clk_get_rate(priv);
  632. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  633. plat->cfg.f_min = mclk /
  634. (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
  635. plat->cfg.f_max = mclk;
  636. if (quirks & TMIO_SD_CAP_16BIT)
  637. plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
  638. else
  639. plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
  640. upriv->mmc = &plat->mmc;
  641. return 0;
  642. }