exynos5-dt.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <dwc3-uboot.h>
  8. #include <fdtdec.h>
  9. #include <asm/io.h>
  10. #include <errno.h>
  11. #include <i2c.h>
  12. #include <mmc.h>
  13. #include <netdev.h>
  14. #include <samsung-usb-phy-uboot.h>
  15. #include <spi.h>
  16. #include <usb.h>
  17. #include <video_bridge.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/dwmmc.h>
  21. #include <asm/arch/mmc.h>
  22. #include <asm/arch/pinmux.h>
  23. #include <asm/arch/power.h>
  24. #include <asm/arch/sromc.h>
  25. #include <power/pmic.h>
  26. #include <power/max77686_pmic.h>
  27. #include <power/regulator.h>
  28. #include <power/s2mps11.h>
  29. #include <power/s5m8767.h>
  30. #include <samsung/exynos5-dt-types.h>
  31. #include <samsung/misc.h>
  32. #include <tmu.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. static void board_enable_audio_codec(void)
  35. {
  36. int node, ret;
  37. struct gpio_desc en_gpio;
  38. node = fdtdec_next_compatible(gd->fdt_blob, 0,
  39. COMPAT_SAMSUNG_EXYNOS5_SOUND);
  40. if (node <= 0)
  41. return;
  42. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  43. "codec-enable-gpio", 0, &en_gpio,
  44. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  45. if (ret == -FDT_ERR_NOTFOUND)
  46. return;
  47. /* Turn on the GPIO which connects to the codec's "enable" line. */
  48. gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE);
  49. #ifdef CONFIG_SOUND_MAX98095
  50. /* Enable MAX98095 Codec */
  51. gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
  52. gpio_direction_output(EXYNOS5_GPIO_X17, 1);
  53. gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
  54. #endif
  55. }
  56. int exynos_init(void)
  57. {
  58. board_enable_audio_codec();
  59. return 0;
  60. }
  61. static int exynos_set_regulator(const char *name, uint uv)
  62. {
  63. struct udevice *dev;
  64. int ret;
  65. ret = regulator_get_by_platname(name, &dev);
  66. if (ret) {
  67. debug("%s: Cannot find regulator %s\n", __func__, name);
  68. return ret;
  69. }
  70. ret = regulator_set_value(dev, uv);
  71. if (ret) {
  72. debug("%s: Cannot set regulator %s\n", __func__, name);
  73. return ret;
  74. }
  75. return 0;
  76. }
  77. int exynos_power_init(void)
  78. {
  79. struct udevice *dev;
  80. int ret;
  81. #ifdef CONFIG_PMIC_S2MPS11
  82. ret = pmic_get("s2mps11_pmic", &dev);
  83. #else
  84. ret = pmic_get("max77686", &dev);
  85. if (!ret) {
  86. /* TODO(sjg@chromium.org): Move into the clock/pmic API */
  87. ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
  88. MAX77686_32KHCP_EN);
  89. if (ret)
  90. return ret;
  91. ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
  92. MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
  93. if (ret)
  94. return ret;
  95. } else {
  96. ret = pmic_get("s5m8767-pmic", &dev);
  97. /* TODO(sjg@chromium.org): Use driver model to access clock */
  98. #ifdef CONFIG_PMIC_S5M8767
  99. if (!ret)
  100. s5m8767_enable_32khz_cp(dev);
  101. #endif
  102. }
  103. #endif /* CONFIG_PMIC_S2MPS11 */
  104. if (ret == -ENODEV)
  105. return 0;
  106. ret = regulators_enable_boot_on(false);
  107. if (ret)
  108. return ret;
  109. ret = exynos_set_regulator("vdd_mif", 1100000);
  110. if (ret)
  111. return ret;
  112. ret = exynos_set_regulator("vdd_arm", 1300000);
  113. if (ret)
  114. return ret;
  115. ret = exynos_set_regulator("vdd_int", 1012500);
  116. if (ret)
  117. return ret;
  118. ret = exynos_set_regulator("vdd_g3d", 1200000);
  119. if (ret)
  120. return ret;
  121. return 0;
  122. }
  123. int board_get_revision(void)
  124. {
  125. return 0;
  126. }
  127. #ifdef CONFIG_USB_DWC3
  128. static struct dwc3_device dwc3_device_data = {
  129. .maximum_speed = USB_SPEED_SUPER,
  130. .base = 0x12400000,
  131. .dr_mode = USB_DR_MODE_PERIPHERAL,
  132. .index = 0,
  133. };
  134. int usb_gadget_handle_interrupts(void)
  135. {
  136. dwc3_uboot_handle_interrupt(0);
  137. return 0;
  138. }
  139. int board_usb_init(int index, enum usb_init_type init)
  140. {
  141. struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
  142. samsung_get_base_usb3_phy();
  143. if (!phy) {
  144. pr_err("usb3 phy not supported\n");
  145. return -ENODEV;
  146. }
  147. set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
  148. exynos5_usb3_phy_init(phy);
  149. return dwc3_uboot_init(&dwc3_device_data);
  150. }
  151. #endif
  152. #ifdef CONFIG_SET_DFU_ALT_INFO
  153. char *get_dfu_alt_system(char *interface, char *devstr)
  154. {
  155. char *info = "Not supported!";
  156. if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2())
  157. return info;
  158. return env_get("dfu_alt_system");
  159. }
  160. char *get_dfu_alt_boot(char *interface, char *devstr)
  161. {
  162. char *info = "Not supported!";
  163. struct mmc *mmc;
  164. char *alt_boot;
  165. int dev_num;
  166. if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2())
  167. return info;
  168. dev_num = simple_strtoul(devstr, NULL, 10);
  169. mmc = find_mmc_device(dev_num);
  170. if (!mmc)
  171. return NULL;
  172. if (mmc_init(mmc))
  173. return NULL;
  174. if (IS_SD(mmc))
  175. alt_boot = CONFIG_DFU_ALT_BOOT_SD;
  176. else
  177. alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
  178. return alt_boot;
  179. }
  180. #endif