max3420_udc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <linux/errno.h>
  4. #include <linux/delay.h>
  5. #include <asm/gpio.h>
  6. #include <linux/list.h>
  7. #include <linux/bitfield.h>
  8. #include <linux/usb/ch9.h>
  9. #include <linux/usb/gadget.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <dm.h>
  13. #include <g_dnl.h>
  14. #define MAX3420_MAX_EPS 4
  15. #define EP_MAX_PACKET 64 /* Same for all Endpoints */
  16. #define EPNAME_SIZE 16 /* Buffer size for endpoint name */
  17. #define MAX3420_SPI_DIR_RD 0 /* read register from MAX3420 */
  18. #define MAX3420_SPI_DIR_WR 1 /* write register to MAX3420 */
  19. /* SPI commands: */
  20. #define MAX3420_SPI_ACK_MASK BIT(0)
  21. #define MAX3420_SPI_DIR_MASK BIT(1)
  22. #define MAX3420_SPI_REG_MASK GENMASK(7, 3)
  23. #define MAX3420_REG_EP0FIFO 0
  24. #define MAX3420_REG_EP1FIFO 1
  25. #define MAX3420_REG_EP2FIFO 2
  26. #define MAX3420_REG_EP3FIFO 3
  27. #define MAX3420_REG_SUDFIFO 4
  28. #define MAX3420_REG_EP0BC 5
  29. #define MAX3420_REG_EP1BC 6
  30. #define MAX3420_REG_EP2BC 7
  31. #define MAX3420_REG_EP3BC 8
  32. #define MAX3420_REG_EPSTALLS 9
  33. #define bACKSTAT BIT(6)
  34. #define bSTLSTAT BIT(5)
  35. #define bSTLEP3IN BIT(4)
  36. #define bSTLEP2IN BIT(3)
  37. #define bSTLEP1OUT BIT(2)
  38. #define bSTLEP0OUT BIT(1)
  39. #define bSTLEP0IN BIT(0)
  40. #define MAX3420_REG_CLRTOGS 10
  41. #define bEP3DISAB BIT(7)
  42. #define bEP2DISAB BIT(6)
  43. #define bEP1DISAB BIT(5)
  44. #define bCTGEP3IN BIT(4)
  45. #define bCTGEP2IN BIT(3)
  46. #define bCTGEP1OUT BIT(2)
  47. #define MAX3420_REG_EPIRQ 11
  48. #define MAX3420_REG_EPIEN 12
  49. #define bSUDAVIRQ BIT(5)
  50. #define bIN3BAVIRQ BIT(4)
  51. #define bIN2BAVIRQ BIT(3)
  52. #define bOUT1DAVIRQ BIT(2)
  53. #define bOUT0DAVIRQ BIT(1)
  54. #define bIN0BAVIRQ BIT(0)
  55. #define MAX3420_REG_USBIRQ 13
  56. #define MAX3420_REG_USBIEN 14
  57. #define bOSCOKIRQ BIT(0)
  58. #define bRWUDNIRQ BIT(1)
  59. #define bBUSACTIRQ BIT(2)
  60. #define bURESIRQ BIT(3)
  61. #define bSUSPIRQ BIT(4)
  62. #define bNOVBUSIRQ BIT(5)
  63. #define bVBUSIRQ BIT(6)
  64. #define bURESDNIRQ BIT(7)
  65. #define MAX3420_REG_USBCTL 15
  66. #define bHOSCSTEN BIT(7)
  67. #define bVBGATE BIT(6)
  68. #define bCHIPRES BIT(5)
  69. #define bPWRDOWN BIT(4)
  70. #define bCONNECT BIT(3)
  71. #define bSIGRWU BIT(2)
  72. #define MAX3420_REG_CPUCTL 16
  73. #define bIE BIT(0)
  74. #define MAX3420_REG_PINCTL 17
  75. #define bEP3INAK BIT(7)
  76. #define bEP2INAK BIT(6)
  77. #define bEP0INAK BIT(5)
  78. #define bFDUPSPI BIT(4)
  79. #define bINTLEVEL BIT(3)
  80. #define bPOSINT BIT(2)
  81. #define bGPXB BIT(1)
  82. #define bGPXA BIT(0)
  83. #define MAX3420_REG_REVISION 18
  84. #define MAX3420_REG_FNADDR 19
  85. #define FNADDR_MASK 0x7f
  86. #define MAX3420_REG_IOPINS 20
  87. #define MAX3420_REG_IOPINS2 21
  88. #define MAX3420_REG_GPINIRQ 22
  89. #define MAX3420_REG_GPINIEN 23
  90. #define MAX3420_REG_GPINPOL 24
  91. #define MAX3420_REG_HIRQ 25
  92. #define MAX3420_REG_HIEN 26
  93. #define MAX3420_REG_MODE 27
  94. #define MAX3420_REG_PERADDR 28
  95. #define MAX3420_REG_HCTL 29
  96. #define MAX3420_REG_HXFR 30
  97. #define MAX3420_REG_HRSL 31
  98. struct max3420_req {
  99. struct usb_request usb_req;
  100. struct list_head queue;
  101. struct max3420_ep *ep;
  102. };
  103. struct max3420_ep {
  104. struct max3420_udc *udc;
  105. struct list_head queue;
  106. char name[EPNAME_SIZE];
  107. unsigned int maxpacket;
  108. struct usb_ep ep_usb;
  109. int halted;
  110. int id;
  111. };
  112. struct max3420_udc {
  113. struct max3420_ep ep[MAX3420_MAX_EPS];
  114. struct usb_gadget_driver *driver;
  115. bool softconnect;
  116. struct usb_ctrlrequest setup;
  117. struct max3420_req ep0req;
  118. struct usb_gadget gadget;
  119. struct spi_slave *slave;
  120. struct udevice *dev;
  121. u8 ep0buf[64];
  122. int remote_wkp;
  123. bool suspended;
  124. };
  125. #define to_max3420_req(r) container_of((r), struct max3420_req, usb_req)
  126. #define to_max3420_ep(e) container_of((e), struct max3420_ep, ep_usb)
  127. #define to_udc(g) container_of((g), struct max3420_udc, gadget)
  128. static void spi_ack_ctrl(struct max3420_udc *udc)
  129. {
  130. struct spi_slave *slave = udc->slave;
  131. u8 txdata[1];
  132. txdata[0] = FIELD_PREP(MAX3420_SPI_ACK_MASK, 1);
  133. spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_ONCE);
  134. }
  135. static u8 spi_rd8_ack(struct max3420_udc *udc, u8 reg, int ackstat)
  136. {
  137. struct spi_slave *slave = udc->slave;
  138. u8 txdata[2], rxdata[2];
  139. txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) |
  140. FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_RD) |
  141. FIELD_PREP(MAX3420_SPI_ACK_MASK, ackstat ? 1 : 0);
  142. rxdata[0] = 0;
  143. rxdata[1] = 0;
  144. spi_xfer(slave, sizeof(txdata), txdata, rxdata, SPI_XFER_ONCE);
  145. return rxdata[1];
  146. }
  147. static u8 spi_rd8(struct max3420_udc *udc, u8 reg)
  148. {
  149. return spi_rd8_ack(udc, reg, 0);
  150. }
  151. static void spi_wr8_ack(struct max3420_udc *udc, u8 reg, u8 val, int ackstat)
  152. {
  153. struct spi_slave *slave = udc->slave;
  154. u8 txdata[2];
  155. txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) |
  156. FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_WR) |
  157. FIELD_PREP(MAX3420_SPI_ACK_MASK, ackstat ? 1 : 0);
  158. txdata[1] = val;
  159. spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_ONCE);
  160. }
  161. static void spi_wr8(struct max3420_udc *udc, u8 reg, u8 val)
  162. {
  163. spi_wr8_ack(udc, reg, val, 0);
  164. }
  165. static void spi_rd_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len)
  166. {
  167. struct spi_slave *slave = udc->slave;
  168. u8 txdata[1];
  169. txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) |
  170. FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_RD);
  171. spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_BEGIN);
  172. spi_xfer(slave, len * 8, NULL, buf, SPI_XFER_END);
  173. }
  174. static void spi_wr_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len)
  175. {
  176. struct spi_slave *slave = udc->slave;
  177. u8 txdata[1];
  178. txdata[0] = FIELD_PREP(MAX3420_SPI_REG_MASK, reg) |
  179. FIELD_PREP(MAX3420_SPI_DIR_MASK, MAX3420_SPI_DIR_WR);
  180. spi_xfer(slave, sizeof(txdata), txdata, NULL, SPI_XFER_BEGIN);
  181. spi_xfer(slave, len * 8, buf, NULL, SPI_XFER_END);
  182. }
  183. /* 0 if not-connected */
  184. int g_dnl_board_usb_cable_connected(void)
  185. {
  186. return 1;
  187. }
  188. static void spi_max3420_enable(struct max3420_ep *ep, int enable)
  189. {
  190. struct max3420_udc *udc = ep->udc;
  191. u8 epdis, epien;
  192. if (ep->id == 0)
  193. return;
  194. epien = spi_rd8(udc, MAX3420_REG_EPIEN);
  195. epdis = spi_rd8(udc, MAX3420_REG_CLRTOGS);
  196. if (enable) {
  197. epdis &= ~BIT(ep->id + 4);
  198. epien |= BIT(ep->id + 1);
  199. } else {
  200. epdis |= BIT(ep->id + 4);
  201. epien &= ~BIT(ep->id + 1);
  202. }
  203. spi_wr8(udc, MAX3420_REG_CLRTOGS, epdis);
  204. spi_wr8(udc, MAX3420_REG_EPIEN, epien);
  205. }
  206. static int
  207. max3420_ep_enable(struct usb_ep *_ep,
  208. const struct usb_endpoint_descriptor *desc)
  209. {
  210. struct max3420_ep *ep = to_max3420_ep(_ep);
  211. _ep->desc = desc;
  212. _ep->maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
  213. spi_max3420_enable(ep, 1);
  214. return 0;
  215. }
  216. static void max3420_req_done(struct max3420_req *req, int status)
  217. {
  218. struct max3420_ep *ep = req->ep;
  219. if (req->usb_req.status == -EINPROGRESS)
  220. req->usb_req.status = status;
  221. else
  222. status = req->usb_req.status;
  223. if (status && status != -ESHUTDOWN)
  224. dev_err(ep->udc->dev, "%s done %p, status %d\n",
  225. ep->ep_usb.name, req, status);
  226. if (req->usb_req.complete)
  227. req->usb_req.complete(&ep->ep_usb, &req->usb_req);
  228. }
  229. static void max3420_ep_nuke(struct max3420_ep *ep, int status)
  230. {
  231. struct max3420_req *req, *r;
  232. list_for_each_entry_safe(req, r, &ep->queue, queue) {
  233. list_del_init(&req->queue);
  234. max3420_req_done(req, status);
  235. }
  236. }
  237. static int max3420_ep_disable(struct usb_ep *_ep)
  238. {
  239. struct max3420_ep *ep = to_max3420_ep(_ep);
  240. _ep->desc = NULL;
  241. max3420_ep_nuke(ep, -ESHUTDOWN);
  242. spi_max3420_enable(ep, 0);
  243. return 0;
  244. }
  245. static struct usb_request *
  246. max3420_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  247. {
  248. struct max3420_ep *ep = to_max3420_ep(_ep);
  249. struct max3420_req *req = kzalloc(sizeof(*req), gfp_flags);
  250. if (!req)
  251. return NULL;
  252. req->ep = ep;
  253. INIT_LIST_HEAD(&req->queue);
  254. return &req->usb_req;
  255. }
  256. static void
  257. max3420_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  258. {
  259. kfree(to_max3420_req(_req));
  260. }
  261. static int
  262. max3420_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  263. {
  264. struct max3420_req *req = to_max3420_req(_req);
  265. struct max3420_ep *ep = to_max3420_ep(_ep);
  266. _req->status = -EINPROGRESS;
  267. _req->actual = 0;
  268. list_add_tail(&req->queue, &ep->queue);
  269. return 0;
  270. }
  271. static int max3420_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  272. {
  273. struct max3420_req *req = to_max3420_req(_req);
  274. list_del_init(&req->queue);
  275. max3420_req_done(req, -ECONNRESET);
  276. return 0;
  277. }
  278. static int max3420_ep_set_halt(struct usb_ep *_ep, int halt)
  279. {
  280. struct max3420_ep *ep = to_max3420_ep(_ep);
  281. struct max3420_udc *udc = ep->udc;
  282. u8 epstalls;
  283. if (ep->id == 0) /* can't stall EP0 */
  284. return 0;
  285. epstalls = spi_rd8(udc, MAX3420_REG_EPSTALLS);
  286. if (halt) {
  287. ep->halted = 1;
  288. epstalls |= BIT(ep->id + 1);
  289. } else {
  290. u8 clrtogs;
  291. ep->halted = 0;
  292. epstalls &= ~BIT(ep->id + 1);
  293. clrtogs = spi_rd8(udc, MAX3420_REG_CLRTOGS);
  294. clrtogs |= BIT(ep->id + 1);
  295. spi_wr8(udc, MAX3420_REG_CLRTOGS, clrtogs);
  296. }
  297. spi_wr8(udc, MAX3420_REG_EPSTALLS, epstalls | bACKSTAT);
  298. return 0;
  299. }
  300. static const struct usb_ep_ops max3420_ep_ops = {
  301. .enable = max3420_ep_enable,
  302. .disable = max3420_ep_disable,
  303. .alloc_request = max3420_ep_alloc_request,
  304. .free_request = max3420_ep_free_request,
  305. .queue = max3420_ep_queue,
  306. .dequeue = max3420_ep_dequeue,
  307. .set_halt = max3420_ep_set_halt,
  308. };
  309. static void __max3420_stop(struct max3420_udc *udc)
  310. {
  311. u8 val;
  312. /* Disable IRQ to CPU */
  313. spi_wr8(udc, MAX3420_REG_CPUCTL, 0);
  314. val = spi_rd8(udc, MAX3420_REG_USBCTL);
  315. val |= bPWRDOWN;
  316. val |= bHOSCSTEN;
  317. spi_wr8(udc, MAX3420_REG_USBCTL, val);
  318. }
  319. static void __max3420_start(struct max3420_udc *udc)
  320. {
  321. u8 val;
  322. /* configure SPI */
  323. spi_wr8(udc, MAX3420_REG_PINCTL, bFDUPSPI);
  324. /* Chip Reset */
  325. spi_wr8(udc, MAX3420_REG_USBCTL, bCHIPRES);
  326. mdelay(5);
  327. spi_wr8(udc, MAX3420_REG_USBCTL, 0);
  328. /* Poll for OSC to stabilize */
  329. while (1) {
  330. val = spi_rd8(udc, MAX3420_REG_USBIRQ);
  331. if (val & bOSCOKIRQ)
  332. break;
  333. cond_resched();
  334. }
  335. /* Enable PULL-UP only when Vbus detected */
  336. val = spi_rd8(udc, MAX3420_REG_USBCTL);
  337. val |= bVBGATE | bCONNECT;
  338. spi_wr8(udc, MAX3420_REG_USBCTL, val);
  339. val = bURESDNIRQ | bURESIRQ;
  340. spi_wr8(udc, MAX3420_REG_USBIEN, val);
  341. /* Enable only EP0 interrupts */
  342. val = bIN0BAVIRQ | bOUT0DAVIRQ | bSUDAVIRQ;
  343. spi_wr8(udc, MAX3420_REG_EPIEN, val);
  344. /* Enable IRQ to CPU */
  345. spi_wr8(udc, MAX3420_REG_CPUCTL, bIE);
  346. }
  347. static int max3420_udc_start(struct usb_gadget *gadget,
  348. struct usb_gadget_driver *driver)
  349. {
  350. struct max3420_udc *udc = to_udc(gadget);
  351. udc->driver = driver;
  352. udc->remote_wkp = 0;
  353. udc->softconnect = true;
  354. __max3420_start(udc);
  355. return 0;
  356. }
  357. static int max3420_udc_stop(struct usb_gadget *gadget)
  358. {
  359. struct max3420_udc *udc = to_udc(gadget);
  360. udc->driver = NULL;
  361. udc->softconnect = false;
  362. __max3420_stop(udc);
  363. return 0;
  364. }
  365. static int max3420_wakeup(struct usb_gadget *gadget)
  366. {
  367. struct max3420_udc *udc = to_udc(gadget);
  368. u8 usbctl;
  369. /* Only if wakeup allowed by host */
  370. if (!udc->remote_wkp || !udc->suspended)
  371. return 0;
  372. /* Set Remote-Wakeup Signal*/
  373. usbctl = spi_rd8(udc, MAX3420_REG_USBCTL);
  374. usbctl |= bSIGRWU;
  375. spi_wr8(udc, MAX3420_REG_USBCTL, usbctl);
  376. mdelay(5);
  377. /* Clear Remote-WkUp Signal*/
  378. usbctl = spi_rd8(udc, MAX3420_REG_USBCTL);
  379. usbctl &= ~bSIGRWU;
  380. spi_wr8(udc, MAX3420_REG_USBCTL, usbctl);
  381. udc->suspended = false;
  382. return 0;
  383. }
  384. static const struct usb_gadget_ops max3420_udc_ops = {
  385. .udc_start = max3420_udc_start,
  386. .udc_stop = max3420_udc_stop,
  387. .wakeup = max3420_wakeup,
  388. };
  389. static struct usb_endpoint_descriptor ep0_desc = {
  390. .bLength = USB_DT_ENDPOINT_SIZE,
  391. .bDescriptorType = USB_DT_ENDPOINT,
  392. .bEndpointAddress = USB_DIR_OUT,
  393. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  394. .wMaxPacketSize = cpu_to_le16(EP_MAX_PACKET),
  395. };
  396. static void max3420_getstatus(struct max3420_udc *udc)
  397. {
  398. struct max3420_ep *ep;
  399. u16 status = 0;
  400. switch (udc->setup.bRequestType & USB_RECIP_MASK) {
  401. case USB_RECIP_DEVICE:
  402. /* Get device status */
  403. status = 0 << USB_DEVICE_SELF_POWERED;
  404. status |= (udc->remote_wkp << USB_DEVICE_REMOTE_WAKEUP);
  405. break;
  406. case USB_RECIP_INTERFACE:
  407. if (udc->driver->setup(&udc->gadget, &udc->setup) < 0)
  408. goto stall;
  409. break;
  410. case USB_RECIP_ENDPOINT:
  411. ep = &udc->ep[udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK];
  412. if (ep->halted)
  413. status = 1 << USB_ENDPOINT_HALT;
  414. break;
  415. default:
  416. goto stall;
  417. }
  418. status = cpu_to_le16(status);
  419. spi_wr_buf(udc, MAX3420_REG_EP0FIFO, &status, 2);
  420. spi_wr8_ack(udc, MAX3420_REG_EP0BC, 2, 1);
  421. return;
  422. stall:
  423. dev_err(udc->dev, "Can't respond to getstatus request\n");
  424. spi_wr8(udc, MAX3420_REG_EPSTALLS, bSTLEP0IN | bSTLEP0OUT | bSTLSTAT);
  425. }
  426. static void max3420_set_clear_feature(struct max3420_udc *udc)
  427. {
  428. int set = udc->setup.bRequest == USB_REQ_SET_FEATURE;
  429. struct max3420_ep *ep;
  430. int id;
  431. switch (udc->setup.bRequestType) {
  432. case USB_RECIP_DEVICE:
  433. if (udc->setup.wValue != USB_DEVICE_REMOTE_WAKEUP)
  434. break;
  435. if (udc->setup.bRequest == USB_REQ_SET_FEATURE)
  436. udc->remote_wkp = 1;
  437. else
  438. udc->remote_wkp = 0;
  439. return spi_ack_ctrl(udc);
  440. case USB_RECIP_ENDPOINT:
  441. if (udc->setup.wValue != USB_ENDPOINT_HALT)
  442. break;
  443. id = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
  444. ep = &udc->ep[id];
  445. max3420_ep_set_halt(&ep->ep_usb, set);
  446. return;
  447. default:
  448. break;
  449. }
  450. dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n");
  451. spi_wr8(udc, MAX3420_REG_EPSTALLS, bSTLEP0IN | bSTLEP0OUT | bSTLSTAT);
  452. }
  453. static void max3420_handle_setup(struct max3420_udc *udc)
  454. {
  455. struct usb_ctrlrequest setup;
  456. u8 addr;
  457. spi_rd_buf(udc, MAX3420_REG_SUDFIFO, (void *)&setup, 8);
  458. udc->setup = setup;
  459. udc->setup.wValue = cpu_to_le16(setup.wValue);
  460. udc->setup.wIndex = cpu_to_le16(setup.wIndex);
  461. udc->setup.wLength = cpu_to_le16(setup.wLength);
  462. switch (udc->setup.bRequest) {
  463. case USB_REQ_GET_STATUS:
  464. /* Data+Status phase form udc */
  465. if ((udc->setup.bRequestType &
  466. (USB_DIR_IN | USB_TYPE_MASK)) !=
  467. (USB_DIR_IN | USB_TYPE_STANDARD)) {
  468. break;
  469. }
  470. return max3420_getstatus(udc);
  471. case USB_REQ_SET_ADDRESS:
  472. /* Status phase from udc */
  473. if (udc->setup.bRequestType != (USB_DIR_OUT |
  474. USB_TYPE_STANDARD | USB_RECIP_DEVICE))
  475. break;
  476. addr = spi_rd8_ack(udc, MAX3420_REG_FNADDR, 1);
  477. dev_dbg(udc->dev, "Assigned Address=%d/%d\n",
  478. udc->setup.wValue, addr);
  479. return;
  480. case USB_REQ_CLEAR_FEATURE:
  481. case USB_REQ_SET_FEATURE:
  482. /* Requests with no data phase, status phase from udc */
  483. if ((udc->setup.bRequestType & USB_TYPE_MASK)
  484. != USB_TYPE_STANDARD)
  485. break;
  486. return max3420_set_clear_feature(udc);
  487. default:
  488. break;
  489. }
  490. if (udc->driver->setup(&udc->gadget, &setup) < 0) {
  491. /* Stall EP0 */
  492. spi_wr8(udc, MAX3420_REG_EPSTALLS,
  493. bSTLEP0IN | bSTLEP0OUT | bSTLSTAT);
  494. }
  495. }
  496. static int do_data(struct max3420_udc *udc, int ep_id, int in)
  497. {
  498. struct max3420_ep *ep = &udc->ep[ep_id];
  499. struct max3420_req *req;
  500. int done, length, psz;
  501. void *buf;
  502. if (list_empty(&ep->queue))
  503. return 0;
  504. req = list_first_entry(&ep->queue, struct max3420_req, queue);
  505. buf = req->usb_req.buf + req->usb_req.actual;
  506. psz = ep->ep_usb.maxpacket;
  507. length = req->usb_req.length - req->usb_req.actual;
  508. length = min(length, psz);
  509. if (length == 0) {
  510. done = 1;
  511. goto xfer_done;
  512. }
  513. done = 0;
  514. if (in) {
  515. spi_wr_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length);
  516. spi_wr8(udc, MAX3420_REG_EP0BC + ep_id, length);
  517. if (length < psz)
  518. done = 1;
  519. } else {
  520. psz = spi_rd8(udc, MAX3420_REG_EP0BC + ep_id);
  521. length = min(length, psz);
  522. spi_rd_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length);
  523. if (length < ep->ep_usb.maxpacket)
  524. done = 1;
  525. }
  526. req->usb_req.actual += length;
  527. if (req->usb_req.actual == req->usb_req.length)
  528. done = 1;
  529. xfer_done:
  530. if (done) {
  531. list_del_init(&req->queue);
  532. if (ep_id == 0)
  533. spi_ack_ctrl(udc);
  534. max3420_req_done(req, 0);
  535. }
  536. return 1;
  537. }
  538. static int max3420_handle_irqs(struct max3420_udc *udc)
  539. {
  540. u8 epien, epirq, usbirq, usbien, reg[4];
  541. int ret = 0;
  542. spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 4);
  543. epirq = reg[0];
  544. epien = reg[1];
  545. usbirq = reg[2];
  546. usbien = reg[3];
  547. usbirq &= usbien;
  548. epirq &= epien;
  549. if (epirq & bSUDAVIRQ) {
  550. spi_wr8(udc, MAX3420_REG_EPIRQ, bSUDAVIRQ);
  551. max3420_handle_setup(udc);
  552. return 1;
  553. }
  554. if (usbirq & bVBUSIRQ) {
  555. spi_wr8(udc, MAX3420_REG_USBIRQ, bVBUSIRQ);
  556. dev_dbg(udc->dev, "Cable plugged in\n");
  557. g_dnl_clear_detach();
  558. return 1;
  559. }
  560. if (usbirq & bNOVBUSIRQ) {
  561. spi_wr8(udc, MAX3420_REG_USBIRQ, bNOVBUSIRQ);
  562. dev_dbg(udc->dev, "Cable pulled out\n");
  563. g_dnl_trigger_detach();
  564. return 1;
  565. }
  566. if (usbirq & bURESIRQ) {
  567. spi_wr8(udc, MAX3420_REG_USBIRQ, bURESIRQ);
  568. return 1;
  569. }
  570. if (usbirq & bURESDNIRQ) {
  571. spi_wr8(udc, MAX3420_REG_USBIRQ, bURESDNIRQ);
  572. spi_wr8(udc, MAX3420_REG_USBIEN, bURESDNIRQ | bURESIRQ);
  573. spi_wr8(udc, MAX3420_REG_EPIEN, bSUDAVIRQ
  574. | bIN0BAVIRQ | bOUT0DAVIRQ);
  575. return 1;
  576. }
  577. if (usbirq & bSUSPIRQ) {
  578. spi_wr8(udc, MAX3420_REG_USBIRQ, bSUSPIRQ);
  579. dev_dbg(udc->dev, "USB Suspend - Enter\n");
  580. udc->suspended = true;
  581. return 1;
  582. }
  583. if (usbirq & bBUSACTIRQ) {
  584. spi_wr8(udc, MAX3420_REG_USBIRQ, bBUSACTIRQ);
  585. dev_dbg(udc->dev, "USB Suspend - Exit\n");
  586. udc->suspended = false;
  587. return 1;
  588. }
  589. if (usbirq & bRWUDNIRQ) {
  590. spi_wr8(udc, MAX3420_REG_USBIRQ, bRWUDNIRQ);
  591. dev_dbg(udc->dev, "Asked Host to wakeup\n");
  592. return 1;
  593. }
  594. if (usbirq & bOSCOKIRQ) {
  595. spi_wr8(udc, MAX3420_REG_USBIRQ, bOSCOKIRQ);
  596. dev_dbg(udc->dev, "Osc stabilized, start work\n");
  597. return 1;
  598. }
  599. if (epirq & bOUT0DAVIRQ && do_data(udc, 0, 0)) {
  600. spi_wr8_ack(udc, MAX3420_REG_EPIRQ, bOUT0DAVIRQ, 1);
  601. ret = 1;
  602. }
  603. if (epirq & bIN0BAVIRQ && do_data(udc, 0, 1))
  604. ret = 1;
  605. if (epirq & bOUT1DAVIRQ && do_data(udc, 1, 0)) {
  606. spi_wr8_ack(udc, MAX3420_REG_EPIRQ, bOUT1DAVIRQ, 1);
  607. ret = 1;
  608. }
  609. if (epirq & bIN2BAVIRQ && do_data(udc, 2, 1))
  610. ret = 1;
  611. if (epirq & bIN3BAVIRQ && do_data(udc, 3, 1))
  612. ret = 1;
  613. return ret;
  614. }
  615. static int max3420_irq(struct max3420_udc *udc)
  616. {
  617. do_data(udc, 0, 1); /* get done with the EP0 ZLP */
  618. return max3420_handle_irqs(udc);
  619. }
  620. static void max3420_setup_eps(struct max3420_udc *udc)
  621. {
  622. int i;
  623. INIT_LIST_HEAD(&udc->gadget.ep_list);
  624. INIT_LIST_HEAD(&udc->ep[0].ep_usb.ep_list);
  625. for (i = 0; i < MAX3420_MAX_EPS; i++) {
  626. struct max3420_ep *ep = &udc->ep[i];
  627. INIT_LIST_HEAD(&ep->queue);
  628. ep->id = i;
  629. ep->udc = udc;
  630. ep->ep_usb.ops = &max3420_ep_ops;
  631. ep->ep_usb.name = ep->name;
  632. ep->ep_usb.maxpacket = EP_MAX_PACKET;
  633. if (i == 0) {
  634. ep->ep_usb.desc = &ep0_desc;
  635. snprintf(ep->name, EPNAME_SIZE, "ep0");
  636. continue;
  637. }
  638. list_add_tail(&ep->ep_usb.ep_list, &udc->gadget.ep_list);
  639. if (i == 1)
  640. snprintf(ep->name, EPNAME_SIZE, "ep1out-bulk");
  641. else
  642. snprintf(ep->name, EPNAME_SIZE, "ep%din-bulk", i);
  643. };
  644. }
  645. static void max3420_setup_spi(struct max3420_udc *udc)
  646. {
  647. u8 reg[8];
  648. spi_claim_bus(udc->slave);
  649. spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 8);
  650. /* configure SPI */
  651. spi_wr8(udc, MAX3420_REG_PINCTL, bFDUPSPI);
  652. }
  653. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  654. {
  655. struct max3420_udc *udc = dev_get_priv(dev);
  656. return max3420_irq(udc);
  657. }
  658. static int max3420_udc_probe(struct udevice *dev)
  659. {
  660. struct max3420_udc *udc = dev_get_priv(dev);
  661. struct dm_spi_slave_platdata *slave_pdata;
  662. struct udevice *bus = dev->parent;
  663. int busnum = bus->seq;
  664. unsigned int cs;
  665. uint speed, mode;
  666. struct udevice *spid;
  667. slave_pdata = dev_get_parent_platdata(dev);
  668. cs = slave_pdata->cs;
  669. speed = slave_pdata->max_hz;
  670. mode = slave_pdata->mode;
  671. spi_get_bus_and_cs(busnum, cs, speed, mode, "spi_generic_drv",
  672. NULL, &spid, &udc->slave);
  673. udc->dev = dev;
  674. udc->gadget.ep0 = &udc->ep[0].ep_usb;
  675. udc->gadget.max_speed = USB_SPEED_FULL;
  676. udc->gadget.speed = USB_SPEED_FULL;
  677. udc->gadget.is_dualspeed = 0;
  678. udc->gadget.ops = &max3420_udc_ops;
  679. udc->gadget.name = "max3420-udc";
  680. max3420_setup_eps(udc);
  681. max3420_setup_spi(udc);
  682. usb_add_gadget_udc((struct device *)dev, &udc->gadget);
  683. return 0;
  684. }
  685. static int max3420_udc_remove(struct udevice *dev)
  686. {
  687. struct max3420_udc *udc = dev_get_priv(dev);
  688. usb_del_gadget_udc(&udc->gadget);
  689. spi_release_bus(udc->slave);
  690. return 0;
  691. }
  692. static const struct udevice_id max3420_ids[] = {
  693. { .compatible = "maxim,max3421-udc" },
  694. { }
  695. };
  696. U_BOOT_DRIVER(max3420_generic_udc) = {
  697. .name = "max3420-udc",
  698. .id = UCLASS_USB_GADGET_GENERIC,
  699. .of_match = max3420_ids,
  700. .probe = max3420_udc_probe,
  701. .remove = max3420_udc_remove,
  702. .priv_auto_alloc_size = sizeof(struct max3420_udc),
  703. };