ci_udc.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <config.h>
  12. #include <cpu_func.h>
  13. #include <net.h>
  14. #include <malloc.h>
  15. #include <asm/byteorder.h>
  16. #include <asm/cache.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/types.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/gadget.h>
  24. #include <usb/ci_udc.h>
  25. #include "../host/ehci.h"
  26. #include "ci_udc.h"
  27. /*
  28. * Check if the system has too long cachelines. If the cachelines are
  29. * longer then 128b, the driver will not be able flush/invalidate data
  30. * cache over separate QH entries. We use 128b because one QH entry is
  31. * 64b long and there are always two QH list entries for each endpoint.
  32. */
  33. #if ARCH_DMA_MINALIGN > 128
  34. #error This driver can not work on systems with caches longer than 128b
  35. #endif
  36. /*
  37. * Every QTD must be individually aligned, since we can program any
  38. * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN,
  39. * and the USB HW requires 32-byte alignment. Align to both:
  40. */
  41. #define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32)
  42. /* Each QTD is this size */
  43. #define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item)
  44. /*
  45. * Align the size of the QTD too, so we can add this value to each
  46. * QTD's address to get another aligned address.
  47. */
  48. #define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN)
  49. /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */
  50. #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ)
  51. #define EP_MAX_LENGTH_TRANSFER 0x4000
  52. #ifndef DEBUG
  53. #define DBG(x...) do {} while (0)
  54. #else
  55. #define DBG(x...) printf(x)
  56. static const char *reqname(unsigned r)
  57. {
  58. switch (r) {
  59. case USB_REQ_GET_STATUS: return "GET_STATUS";
  60. case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
  61. case USB_REQ_SET_FEATURE: return "SET_FEATURE";
  62. case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
  63. case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
  64. case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
  65. case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
  66. case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
  67. case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
  68. case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
  69. default: return "*UNKNOWN*";
  70. }
  71. }
  72. #endif
  73. static struct usb_endpoint_descriptor ep0_desc = {
  74. .bLength = sizeof(struct usb_endpoint_descriptor),
  75. .bDescriptorType = USB_DT_ENDPOINT,
  76. .bEndpointAddress = USB_DIR_IN,
  77. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  78. };
  79. static int ci_pullup(struct usb_gadget *gadget, int is_on);
  80. static int ci_ep_enable(struct usb_ep *ep,
  81. const struct usb_endpoint_descriptor *desc);
  82. static int ci_ep_disable(struct usb_ep *ep);
  83. static int ci_ep_queue(struct usb_ep *ep,
  84. struct usb_request *req, gfp_t gfp_flags);
  85. static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req);
  86. static struct usb_request *
  87. ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
  88. static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
  89. static struct usb_gadget_ops ci_udc_ops = {
  90. .pullup = ci_pullup,
  91. };
  92. static struct usb_ep_ops ci_ep_ops = {
  93. .enable = ci_ep_enable,
  94. .disable = ci_ep_disable,
  95. .queue = ci_ep_queue,
  96. .dequeue = ci_ep_dequeue,
  97. .alloc_request = ci_ep_alloc_request,
  98. .free_request = ci_ep_free_request,
  99. };
  100. __weak void ci_init_after_reset(struct ehci_ctrl *ctrl)
  101. {
  102. }
  103. /* Init values for USB endpoints. */
  104. static const struct usb_ep ci_ep_init[5] = {
  105. [0] = { /* EP 0 */
  106. .maxpacket = 64,
  107. .name = "ep0",
  108. .ops = &ci_ep_ops,
  109. },
  110. [1] = {
  111. .maxpacket = 512,
  112. .name = "ep1in-bulk",
  113. .ops = &ci_ep_ops,
  114. },
  115. [2] = {
  116. .maxpacket = 512,
  117. .name = "ep2out-bulk",
  118. .ops = &ci_ep_ops,
  119. },
  120. [3] = {
  121. .maxpacket = 512,
  122. .name = "ep3in-int",
  123. .ops = &ci_ep_ops,
  124. },
  125. [4] = {
  126. .maxpacket = 512,
  127. .name = "ep-",
  128. .ops = &ci_ep_ops,
  129. },
  130. };
  131. static struct ci_drv controller = {
  132. .gadget = {
  133. .name = "ci_udc",
  134. .ops = &ci_udc_ops,
  135. .is_dualspeed = 1,
  136. },
  137. };
  138. /**
  139. * ci_get_qh() - return queue head for endpoint
  140. * @ep_num: Endpoint number
  141. * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
  142. *
  143. * This function returns the QH associated with particular endpoint
  144. * and it's direction.
  145. */
  146. static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
  147. {
  148. return &controller.epts[(ep_num * 2) + dir_in];
  149. }
  150. /**
  151. * ci_get_qtd() - return queue item for endpoint
  152. * @ep_num: Endpoint number
  153. * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
  154. *
  155. * This function returns the QH associated with particular endpoint
  156. * and it's direction.
  157. */
  158. static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
  159. {
  160. int index = (ep_num * 2) + dir_in;
  161. uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ);
  162. return (struct ept_queue_item *)imem;
  163. }
  164. /**
  165. * ci_flush_qh - flush cache over queue head
  166. * @ep_num: Endpoint number
  167. *
  168. * This function flushes cache over QH for particular endpoint.
  169. */
  170. static void ci_flush_qh(int ep_num)
  171. {
  172. struct ept_queue_head *head = ci_get_qh(ep_num, 0);
  173. const unsigned long start = (unsigned long)head;
  174. const unsigned long end = start + 2 * sizeof(*head);
  175. flush_dcache_range(start, end);
  176. }
  177. /**
  178. * ci_invalidate_qh - invalidate cache over queue head
  179. * @ep_num: Endpoint number
  180. *
  181. * This function invalidates cache over QH for particular endpoint.
  182. */
  183. static void ci_invalidate_qh(int ep_num)
  184. {
  185. struct ept_queue_head *head = ci_get_qh(ep_num, 0);
  186. unsigned long start = (unsigned long)head;
  187. unsigned long end = start + 2 * sizeof(*head);
  188. invalidate_dcache_range(start, end);
  189. }
  190. /**
  191. * ci_flush_qtd - flush cache over queue item
  192. * @ep_num: Endpoint number
  193. *
  194. * This function flushes cache over qTD pair for particular endpoint.
  195. */
  196. static void ci_flush_qtd(int ep_num)
  197. {
  198. struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
  199. const unsigned long start = (unsigned long)item;
  200. const unsigned long end = start + 2 * ILIST_ENT_SZ;
  201. flush_dcache_range(start, end);
  202. }
  203. /**
  204. * ci_flush_td - flush cache over queue item
  205. * @td: td pointer
  206. *
  207. * This function flushes cache for particular transfer descriptor.
  208. */
  209. static void ci_flush_td(struct ept_queue_item *td)
  210. {
  211. const unsigned long start = (unsigned long)td;
  212. const unsigned long end = (unsigned long)td + ILIST_ENT_SZ;
  213. flush_dcache_range(start, end);
  214. }
  215. /**
  216. * ci_invalidate_qtd - invalidate cache over queue item
  217. * @ep_num: Endpoint number
  218. *
  219. * This function invalidates cache over qTD pair for particular endpoint.
  220. */
  221. static void ci_invalidate_qtd(int ep_num)
  222. {
  223. struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
  224. const unsigned long start = (unsigned long)item;
  225. const unsigned long end = start + 2 * ILIST_ENT_SZ;
  226. invalidate_dcache_range(start, end);
  227. }
  228. /**
  229. * ci_invalidate_td - invalidate cache over queue item
  230. * @td: td pointer
  231. *
  232. * This function invalidates cache for particular transfer descriptor.
  233. */
  234. static void ci_invalidate_td(struct ept_queue_item *td)
  235. {
  236. const unsigned long start = (unsigned long)td;
  237. const unsigned long end = start + ILIST_ENT_SZ;
  238. invalidate_dcache_range(start, end);
  239. }
  240. static struct usb_request *
  241. ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
  242. {
  243. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  244. int num = -1;
  245. struct ci_req *ci_req;
  246. if (ci_ep->desc)
  247. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  248. if (num == 0 && controller.ep0_req)
  249. return &controller.ep0_req->req;
  250. ci_req = calloc(1, sizeof(*ci_req));
  251. if (!ci_req)
  252. return NULL;
  253. INIT_LIST_HEAD(&ci_req->queue);
  254. if (num == 0)
  255. controller.ep0_req = ci_req;
  256. return &ci_req->req;
  257. }
  258. static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
  259. {
  260. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  261. struct ci_req *ci_req = container_of(req, struct ci_req, req);
  262. int num = -1;
  263. if (ci_ep->desc)
  264. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  265. if (num == 0) {
  266. if (!controller.ep0_req)
  267. return;
  268. controller.ep0_req = 0;
  269. }
  270. if (ci_req->b_buf)
  271. free(ci_req->b_buf);
  272. free(ci_req);
  273. }
  274. static void ep_enable(int num, int in, int maxpacket)
  275. {
  276. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  277. unsigned n;
  278. n = readl(&udc->epctrl[num]);
  279. if (in)
  280. n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
  281. else
  282. n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
  283. if (num != 0) {
  284. struct ept_queue_head *head = ci_get_qh(num, in);
  285. head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
  286. ci_flush_qh(num);
  287. }
  288. writel(n, &udc->epctrl[num]);
  289. }
  290. static int ci_ep_enable(struct usb_ep *ep,
  291. const struct usb_endpoint_descriptor *desc)
  292. {
  293. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  294. int num, in;
  295. num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  296. in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
  297. ci_ep->desc = desc;
  298. if (num) {
  299. int max = get_unaligned_le16(&desc->wMaxPacketSize);
  300. if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
  301. max = 64;
  302. if (ep->maxpacket != max) {
  303. DBG("%s: from %d to %d\n", __func__,
  304. ep->maxpacket, max);
  305. ep->maxpacket = max;
  306. }
  307. }
  308. ep_enable(num, in, ep->maxpacket);
  309. DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
  310. return 0;
  311. }
  312. static int ci_ep_disable(struct usb_ep *ep)
  313. {
  314. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  315. ci_ep->desc = NULL;
  316. return 0;
  317. }
  318. static int ci_bounce(struct ci_req *ci_req, int in)
  319. {
  320. struct usb_request *req = &ci_req->req;
  321. unsigned long addr = (unsigned long)req->buf;
  322. unsigned long hwaddr;
  323. uint32_t aligned_used_len;
  324. /* Input buffer address is not aligned. */
  325. if (addr & (ARCH_DMA_MINALIGN - 1))
  326. goto align;
  327. /* Input buffer length is not aligned. */
  328. if (req->length & (ARCH_DMA_MINALIGN - 1))
  329. goto align;
  330. /* The buffer is well aligned, only flush cache. */
  331. ci_req->hw_len = req->length;
  332. ci_req->hw_buf = req->buf;
  333. goto flush;
  334. align:
  335. if (ci_req->b_buf && req->length > ci_req->b_len) {
  336. free(ci_req->b_buf);
  337. ci_req->b_buf = 0;
  338. }
  339. if (!ci_req->b_buf) {
  340. ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN);
  341. ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len);
  342. if (!ci_req->b_buf)
  343. return -ENOMEM;
  344. }
  345. ci_req->hw_len = ci_req->b_len;
  346. ci_req->hw_buf = ci_req->b_buf;
  347. if (in)
  348. memcpy(ci_req->hw_buf, req->buf, req->length);
  349. flush:
  350. hwaddr = (unsigned long)ci_req->hw_buf;
  351. aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
  352. flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
  353. return 0;
  354. }
  355. static void ci_debounce(struct ci_req *ci_req, int in)
  356. {
  357. struct usb_request *req = &ci_req->req;
  358. unsigned long addr = (unsigned long)req->buf;
  359. unsigned long hwaddr = (unsigned long)ci_req->hw_buf;
  360. uint32_t aligned_used_len;
  361. if (in)
  362. return;
  363. aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
  364. invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len);
  365. if (addr == hwaddr)
  366. return; /* not a bounce */
  367. memcpy(req->buf, ci_req->hw_buf, req->actual);
  368. }
  369. static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
  370. {
  371. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  372. struct ept_queue_item *item;
  373. struct ept_queue_head *head;
  374. int bit, num, len, in;
  375. struct ci_req *ci_req;
  376. u8 *buf;
  377. uint32_t len_left, len_this_dtd;
  378. struct ept_queue_item *dtd, *qtd;
  379. ci_ep->req_primed = true;
  380. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  381. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  382. item = ci_get_qtd(num, in);
  383. head = ci_get_qh(num, in);
  384. ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
  385. len = ci_req->req.length;
  386. head->next = (unsigned long)item;
  387. head->info = 0;
  388. ci_req->dtd_count = 0;
  389. buf = ci_req->hw_buf;
  390. len_left = len;
  391. dtd = item;
  392. do {
  393. len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER);
  394. dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE;
  395. dtd->page0 = (unsigned long)buf;
  396. dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000;
  397. dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000;
  398. dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000;
  399. dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000;
  400. len_left -= len_this_dtd;
  401. buf += len_this_dtd;
  402. if (len_left) {
  403. qtd = (struct ept_queue_item *)
  404. memalign(ILIST_ALIGN, ILIST_ENT_SZ);
  405. dtd->next = (unsigned long)qtd;
  406. dtd = qtd;
  407. memset(dtd, 0, ILIST_ENT_SZ);
  408. }
  409. ci_req->dtd_count++;
  410. } while (len_left);
  411. item = dtd;
  412. /*
  413. * When sending the data for an IN transaction, the attached host
  414. * knows that all data for the IN is sent when one of the following
  415. * occurs:
  416. * a) A zero-length packet is transmitted.
  417. * b) A packet with length that isn't an exact multiple of the ep's
  418. * maxpacket is transmitted.
  419. * c) Enough data is sent to exactly fill the host's maximum expected
  420. * IN transaction size.
  421. *
  422. * One of these conditions MUST apply at the end of an IN transaction,
  423. * or the transaction will not be considered complete by the host. If
  424. * none of (a)..(c) already applies, then we must force (a) to apply
  425. * by explicitly sending an extra zero-length packet.
  426. */
  427. /* IN !a !b !c */
  428. if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) {
  429. /*
  430. * Each endpoint has 2 items allocated, even though typically
  431. * only 1 is used at a time since either an IN or an OUT but
  432. * not both is queued. For an IN transaction, item currently
  433. * points at the second of these items, so we know that we
  434. * can use the other to transmit the extra zero-length packet.
  435. */
  436. struct ept_queue_item *other_item = ci_get_qtd(num, 0);
  437. item->next = (unsigned long)other_item;
  438. item = other_item;
  439. item->info = INFO_ACTIVE;
  440. }
  441. item->next = TERMINATE;
  442. item->info |= INFO_IOC;
  443. ci_flush_qtd(num);
  444. item = (struct ept_queue_item *)(unsigned long)head->next;
  445. while (item->next != TERMINATE) {
  446. ci_flush_td((struct ept_queue_item *)(unsigned long)item->next);
  447. item = (struct ept_queue_item *)(unsigned long)item->next;
  448. }
  449. DBG("ept%d %s queue len %x, req %p, buffer %p\n",
  450. num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
  451. ci_flush_qh(num);
  452. if (in)
  453. bit = EPT_TX(num);
  454. else
  455. bit = EPT_RX(num);
  456. writel(bit, &udc->epprime);
  457. }
  458. static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  459. {
  460. struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep);
  461. struct ci_req *ci_req;
  462. list_for_each_entry(ci_req, &ci_ep->queue, queue) {
  463. if (&ci_req->req == _req)
  464. break;
  465. }
  466. if (&ci_req->req != _req)
  467. return -EINVAL;
  468. list_del_init(&ci_req->queue);
  469. if (ci_req->req.status == -EINPROGRESS) {
  470. ci_req->req.status = -ECONNRESET;
  471. if (ci_req->req.complete)
  472. ci_req->req.complete(_ep, _req);
  473. }
  474. return 0;
  475. }
  476. static int ci_ep_queue(struct usb_ep *ep,
  477. struct usb_request *req, gfp_t gfp_flags)
  478. {
  479. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  480. struct ci_req *ci_req = container_of(req, struct ci_req, req);
  481. int in, ret;
  482. int __maybe_unused num;
  483. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  484. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  485. if (!num && ci_ep->req_primed) {
  486. /*
  487. * The flipping of ep0 between IN and OUT relies on
  488. * ci_ep_queue consuming the current IN/OUT setting
  489. * immediately. If this is deferred to a later point when the
  490. * req is pulled out of ci_req->queue, then the IN/OUT setting
  491. * may have been changed since the req was queued, and state
  492. * will get out of sync. This condition doesn't occur today,
  493. * but could if bugs were introduced later, and this error
  494. * check will save a lot of debugging time.
  495. */
  496. printf("%s: ep0 transaction already in progress\n", __func__);
  497. return -EPROTO;
  498. }
  499. ret = ci_bounce(ci_req, in);
  500. if (ret)
  501. return ret;
  502. DBG("ept%d %s pre-queue req %p, buffer %p\n",
  503. num, in ? "in" : "out", ci_req, ci_req->hw_buf);
  504. list_add_tail(&ci_req->queue, &ci_ep->queue);
  505. if (!ci_ep->req_primed)
  506. ci_ep_submit_next_request(ci_ep);
  507. return 0;
  508. }
  509. static void flip_ep0_direction(void)
  510. {
  511. if (ep0_desc.bEndpointAddress == USB_DIR_IN) {
  512. DBG("%s: Flipping ep0 to OUT\n", __func__);
  513. ep0_desc.bEndpointAddress = 0;
  514. } else {
  515. DBG("%s: Flipping ep0 to IN\n", __func__);
  516. ep0_desc.bEndpointAddress = USB_DIR_IN;
  517. }
  518. }
  519. static void handle_ep_complete(struct ci_ep *ci_ep)
  520. {
  521. struct ept_queue_item *item, *next_td;
  522. int num, in, len, j;
  523. struct ci_req *ci_req;
  524. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  525. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  526. item = ci_get_qtd(num, in);
  527. ci_invalidate_qtd(num);
  528. ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
  529. next_td = item;
  530. len = 0;
  531. for (j = 0; j < ci_req->dtd_count; j++) {
  532. ci_invalidate_td(next_td);
  533. item = next_td;
  534. len += (item->info >> 16) & 0x7fff;
  535. if (item->info & 0xff)
  536. printf("EP%d/%s FAIL info=%x pg0=%x\n",
  537. num, in ? "in" : "out", item->info, item->page0);
  538. if (j != ci_req->dtd_count - 1)
  539. next_td = (struct ept_queue_item *)(unsigned long)
  540. item->next;
  541. if (j != 0)
  542. free(item);
  543. }
  544. list_del_init(&ci_req->queue);
  545. ci_ep->req_primed = false;
  546. if (!list_empty(&ci_ep->queue))
  547. ci_ep_submit_next_request(ci_ep);
  548. ci_req->req.actual = ci_req->req.length - len;
  549. ci_debounce(ci_req, in);
  550. DBG("ept%d %s req %p, complete %x\n",
  551. num, in ? "in" : "out", ci_req, len);
  552. if (num != 0 || controller.ep0_data_phase)
  553. ci_req->req.complete(&ci_ep->ep, &ci_req->req);
  554. if (num == 0 && controller.ep0_data_phase) {
  555. /*
  556. * Data Stage is complete, so flip ep0 dir for Status Stage,
  557. * which always transfers a packet in the opposite direction.
  558. */
  559. DBG("%s: flip ep0 dir for Status Stage\n", __func__);
  560. flip_ep0_direction();
  561. controller.ep0_data_phase = false;
  562. ci_req->req.length = 0;
  563. usb_ep_queue(&ci_ep->ep, &ci_req->req, 0);
  564. }
  565. }
  566. #define SETUP(type, request) (((type) << 8) | (request))
  567. static void handle_setup(void)
  568. {
  569. struct ci_ep *ci_ep = &controller.ep[0];
  570. struct ci_req *ci_req;
  571. struct usb_request *req;
  572. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  573. struct ept_queue_head *head;
  574. struct usb_ctrlrequest r;
  575. int status = 0;
  576. int num, in, _num, _in, i;
  577. char *buf;
  578. ci_req = controller.ep0_req;
  579. req = &ci_req->req;
  580. head = ci_get_qh(0, 0); /* EP0 OUT */
  581. ci_invalidate_qh(0);
  582. memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
  583. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  584. writel(EPT_RX(0), &udc->epsetupstat);
  585. #else
  586. writel(EPT_RX(0), &udc->epstat);
  587. #endif
  588. DBG("handle setup %s, %x, %x index %x value %x length %x\n",
  589. reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex,
  590. r.wValue, r.wLength);
  591. /* Set EP0 dir for Data Stage based on Setup Stage data */
  592. if (r.bRequestType & USB_DIR_IN) {
  593. DBG("%s: Set ep0 to IN for Data Stage\n", __func__);
  594. ep0_desc.bEndpointAddress = USB_DIR_IN;
  595. } else {
  596. DBG("%s: Set ep0 to OUT for Data Stage\n", __func__);
  597. ep0_desc.bEndpointAddress = 0;
  598. }
  599. if (r.wLength) {
  600. controller.ep0_data_phase = true;
  601. } else {
  602. /* 0 length -> no Data Stage. Flip dir for Status Stage */
  603. DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__);
  604. flip_ep0_direction();
  605. controller.ep0_data_phase = false;
  606. }
  607. list_del_init(&ci_req->queue);
  608. ci_ep->req_primed = false;
  609. switch (SETUP(r.bRequestType, r.bRequest)) {
  610. case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
  611. _num = r.wIndex & 15;
  612. _in = !!(r.wIndex & 0x80);
  613. if ((r.wValue == 0) && (r.wLength == 0)) {
  614. req->length = 0;
  615. for (i = 0; i < NUM_ENDPOINTS; i++) {
  616. struct ci_ep *ep = &controller.ep[i];
  617. if (!ep->desc)
  618. continue;
  619. num = ep->desc->bEndpointAddress
  620. & USB_ENDPOINT_NUMBER_MASK;
  621. in = (ep->desc->bEndpointAddress
  622. & USB_DIR_IN) != 0;
  623. if ((num == _num) && (in == _in)) {
  624. ep_enable(num, in, ep->ep.maxpacket);
  625. usb_ep_queue(controller.gadget.ep0,
  626. req, 0);
  627. break;
  628. }
  629. }
  630. }
  631. return;
  632. case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
  633. /*
  634. * write address delayed (will take effect
  635. * after the next IN txn)
  636. */
  637. writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
  638. req->length = 0;
  639. usb_ep_queue(controller.gadget.ep0, req, 0);
  640. return;
  641. case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
  642. req->length = 2;
  643. buf = (char *)req->buf;
  644. buf[0] = 1 << USB_DEVICE_SELF_POWERED;
  645. buf[1] = 0;
  646. usb_ep_queue(controller.gadget.ep0, req, 0);
  647. return;
  648. }
  649. /* pass request up to the gadget driver */
  650. if (controller.driver)
  651. status = controller.driver->setup(&controller.gadget, &r);
  652. else
  653. status = -ENODEV;
  654. if (!status)
  655. return;
  656. DBG("STALL reqname %s type %x value %x, index %x\n",
  657. reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
  658. writel((1<<16) | (1 << 0), &udc->epctrl[0]);
  659. }
  660. static void stop_activity(void)
  661. {
  662. int i, num, in;
  663. struct ept_queue_head *head;
  664. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  665. writel(readl(&udc->epcomp), &udc->epcomp);
  666. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  667. writel(readl(&udc->epsetupstat), &udc->epsetupstat);
  668. #endif
  669. writel(readl(&udc->epstat), &udc->epstat);
  670. writel(0xffffffff, &udc->epflush);
  671. /* error out any pending reqs */
  672. for (i = 0; i < NUM_ENDPOINTS; i++) {
  673. if (i != 0)
  674. writel(0, &udc->epctrl[i]);
  675. if (controller.ep[i].desc) {
  676. num = controller.ep[i].desc->bEndpointAddress
  677. & USB_ENDPOINT_NUMBER_MASK;
  678. in = (controller.ep[i].desc->bEndpointAddress
  679. & USB_DIR_IN) != 0;
  680. head = ci_get_qh(num, in);
  681. head->info = INFO_ACTIVE;
  682. ci_flush_qh(num);
  683. }
  684. }
  685. }
  686. void udc_irq(void)
  687. {
  688. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  689. unsigned n = readl(&udc->usbsts);
  690. writel(n, &udc->usbsts);
  691. int bit, i, num, in;
  692. n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
  693. if (n == 0)
  694. return;
  695. if (n & STS_URI) {
  696. DBG("-- reset --\n");
  697. stop_activity();
  698. }
  699. if (n & STS_SLI)
  700. DBG("-- suspend --\n");
  701. if (n & STS_PCI) {
  702. int max = 64;
  703. int speed = USB_SPEED_FULL;
  704. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  705. bit = (readl(&udc->hostpc1_devlc) >> 25) & 3;
  706. #else
  707. bit = (readl(&udc->portsc) >> 26) & 3;
  708. #endif
  709. DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
  710. if (bit == 2) {
  711. speed = USB_SPEED_HIGH;
  712. max = 512;
  713. }
  714. controller.gadget.speed = speed;
  715. for (i = 1; i < NUM_ENDPOINTS; i++) {
  716. if (controller.ep[i].ep.maxpacket > max)
  717. controller.ep[i].ep.maxpacket = max;
  718. }
  719. }
  720. if (n & STS_UEI)
  721. printf("<UEI %x>\n", readl(&udc->epcomp));
  722. if ((n & STS_UI) || (n & STS_UEI)) {
  723. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  724. n = readl(&udc->epsetupstat);
  725. #else
  726. n = readl(&udc->epstat);
  727. #endif
  728. if (n & EPT_RX(0))
  729. handle_setup();
  730. n = readl(&udc->epcomp);
  731. if (n != 0)
  732. writel(n, &udc->epcomp);
  733. for (i = 0; i < NUM_ENDPOINTS && n; i++) {
  734. if (controller.ep[i].desc) {
  735. num = controller.ep[i].desc->bEndpointAddress
  736. & USB_ENDPOINT_NUMBER_MASK;
  737. in = (controller.ep[i].desc->bEndpointAddress
  738. & USB_DIR_IN) != 0;
  739. bit = (in) ? EPT_TX(num) : EPT_RX(num);
  740. if (n & bit)
  741. handle_ep_complete(&controller.ep[i]);
  742. }
  743. }
  744. }
  745. }
  746. int usb_gadget_handle_interrupts(int index)
  747. {
  748. u32 value;
  749. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  750. value = readl(&udc->usbsts);
  751. if (value)
  752. udc_irq();
  753. return value;
  754. }
  755. void udc_disconnect(void)
  756. {
  757. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  758. /* disable pullup */
  759. stop_activity();
  760. writel(USBCMD_FS2, &udc->usbcmd);
  761. udelay(800);
  762. if (controller.driver)
  763. controller.driver->disconnect(&controller.gadget);
  764. }
  765. static int ci_pullup(struct usb_gadget *gadget, int is_on)
  766. {
  767. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  768. if (is_on) {
  769. /* RESET */
  770. writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
  771. udelay(200);
  772. ci_init_after_reset(controller.ctrl);
  773. writel((unsigned long)controller.epts, &udc->epinitaddr);
  774. /* select DEVICE mode */
  775. writel(USBMODE_DEVICE, &udc->usbmode);
  776. #if !defined(CONFIG_USB_GADGET_DUALSPEED)
  777. /* Port force Full-Speed Connect */
  778. setbits_le32(&udc->portsc, PFSC);
  779. #endif
  780. writel(0xffffffff, &udc->epflush);
  781. /* Turn on the USB connection by enabling the pullup resistor */
  782. setbits_le32(&udc->usbcmd, USBCMD_ITC(MICRO_8FRAME) |
  783. USBCMD_RUN);
  784. } else {
  785. udc_disconnect();
  786. }
  787. return 0;
  788. }
  789. static int ci_udc_probe(void)
  790. {
  791. struct ept_queue_head *head;
  792. int i;
  793. const int num = 2 * NUM_ENDPOINTS;
  794. const int eplist_min_align = 4096;
  795. const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
  796. const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
  797. const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
  798. /* The QH list must be aligned to 4096 bytes. */
  799. controller.epts = memalign(eplist_align, eplist_sz);
  800. if (!controller.epts)
  801. return -ENOMEM;
  802. memset(controller.epts, 0, eplist_sz);
  803. controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
  804. if (!controller.items_mem) {
  805. free(controller.epts);
  806. return -ENOMEM;
  807. }
  808. memset(controller.items_mem, 0, ILIST_SZ);
  809. for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
  810. /*
  811. * Configure QH for each endpoint. The structure of the QH list
  812. * is such that each two subsequent fields, N and N+1 where N is
  813. * even, in the QH list represent QH for one endpoint. The Nth
  814. * entry represents OUT configuration and the N+1th entry does
  815. * represent IN configuration of the endpoint.
  816. */
  817. head = controller.epts + i;
  818. if (i < 2)
  819. head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
  820. | CONFIG_ZLT | CONFIG_IOS;
  821. else
  822. head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
  823. | CONFIG_ZLT;
  824. head->next = TERMINATE;
  825. head->info = 0;
  826. if (i & 1) {
  827. ci_flush_qh(i / 2);
  828. ci_flush_qtd(i / 2);
  829. }
  830. }
  831. INIT_LIST_HEAD(&controller.gadget.ep_list);
  832. /* Init EP 0 */
  833. memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
  834. controller.ep[0].desc = &ep0_desc;
  835. INIT_LIST_HEAD(&controller.ep[0].queue);
  836. controller.ep[0].req_primed = false;
  837. controller.gadget.ep0 = &controller.ep[0].ep;
  838. INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
  839. /* Init EP 1..3 */
  840. for (i = 1; i < 4; i++) {
  841. memcpy(&controller.ep[i].ep, &ci_ep_init[i],
  842. sizeof(*ci_ep_init));
  843. INIT_LIST_HEAD(&controller.ep[i].queue);
  844. controller.ep[i].req_primed = false;
  845. list_add_tail(&controller.ep[i].ep.ep_list,
  846. &controller.gadget.ep_list);
  847. }
  848. /* Init EP 4..n */
  849. for (i = 4; i < NUM_ENDPOINTS; i++) {
  850. memcpy(&controller.ep[i].ep, &ci_ep_init[4],
  851. sizeof(*ci_ep_init));
  852. INIT_LIST_HEAD(&controller.ep[i].queue);
  853. controller.ep[i].req_primed = false;
  854. list_add_tail(&controller.ep[i].ep.ep_list,
  855. &controller.gadget.ep_list);
  856. }
  857. ci_ep_alloc_request(&controller.ep[0].ep, 0);
  858. if (!controller.ep0_req) {
  859. free(controller.items_mem);
  860. free(controller.epts);
  861. return -ENOMEM;
  862. }
  863. return 0;
  864. }
  865. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  866. {
  867. int ret;
  868. if (!driver)
  869. return -EINVAL;
  870. if (!driver->bind || !driver->setup || !driver->disconnect)
  871. return -EINVAL;
  872. if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
  873. return -EINVAL;
  874. #if CONFIG_IS_ENABLED(DM_USB)
  875. ret = usb_setup_ehci_gadget(&controller.ctrl);
  876. #else
  877. ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
  878. #endif
  879. if (ret)
  880. return ret;
  881. ret = ci_udc_probe();
  882. if (ret) {
  883. DBG("udc probe failed, returned %d\n", ret);
  884. return ret;
  885. }
  886. ret = driver->bind(&controller.gadget);
  887. if (ret) {
  888. DBG("driver->bind() returned %d\n", ret);
  889. return ret;
  890. }
  891. controller.driver = driver;
  892. return 0;
  893. }
  894. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  895. {
  896. udc_disconnect();
  897. driver->unbind(&controller.gadget);
  898. controller.driver = NULL;
  899. ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
  900. free(controller.items_mem);
  901. free(controller.epts);
  902. #if CONFIG_IS_ENABLED(DM_USB)
  903. usb_remove_ehci_gadget(&controller.ctrl);
  904. #else
  905. usb_lowlevel_stop(0);
  906. controller.ctrl = NULL;
  907. #endif
  908. return 0;
  909. }
  910. bool dfu_usb_get_reset(void)
  911. {
  912. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  913. return !!(readl(&udc->usbsts) & STS_URI);
  914. }