r8152.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. */
  6. #ifndef _RTL8152_ETH_H
  7. #define _RTL8152_ETH_H
  8. #include <linux/bitops.h>
  9. #define R8152_BASE_NAME "r8152"
  10. #define PLA_IDR 0xc000
  11. #define PLA_RCR 0xc010
  12. #define PLA_RMS 0xc016
  13. #define PLA_RXFIFO_CTRL0 0xc0a0
  14. #define PLA_RXFIFO_CTRL1 0xc0a4
  15. #define PLA_RXFIFO_CTRL2 0xc0a8
  16. #define PLA_DMY_REG0 0xc0b0
  17. #define PLA_FMC 0xc0b4
  18. #define PLA_CFG_WOL 0xc0b6
  19. #define PLA_TEREDO_CFG 0xc0bc
  20. #define PLA_MAR 0xcd00
  21. #define PLA_BACKUP 0xd000
  22. #define PLA_BDC_CR 0xd1a0
  23. #define PLA_TEREDO_TIMER 0xd2cc
  24. #define PLA_REALWOW_TIMER 0xd2e8
  25. #define PLA_EXTRA_STATUS 0xd398
  26. #define PLA_EFUSE_DATA 0xdd00
  27. #define PLA_EFUSE_CMD 0xdd02
  28. #define PLA_LEDSEL 0xdd90
  29. #define PLA_LED_FEATURE 0xdd92
  30. #define PLA_PHYAR 0xde00
  31. #define PLA_BOOT_CTRL 0xe004
  32. #define PLA_GPHY_INTR_IMR 0xe022
  33. #define PLA_EEE_CR 0xe040
  34. #define PLA_EEEP_CR 0xe080
  35. #define PLA_MAC_PWR_CTRL 0xe0c0
  36. #define PLA_MAC_PWR_CTRL2 0xe0ca
  37. #define PLA_MAC_PWR_CTRL3 0xe0cc
  38. #define PLA_MAC_PWR_CTRL4 0xe0ce
  39. #define PLA_WDT6_CTRL 0xe428
  40. #define PLA_TCR0 0xe610
  41. #define PLA_TCR1 0xe612
  42. #define PLA_MTPS 0xe615
  43. #define PLA_TXFIFO_CTRL 0xe618
  44. #define PLA_RSTTALLY 0xe800
  45. #define BIST_CTRL 0xe810
  46. #define PLA_CR 0xe813
  47. #define PLA_CRWECR 0xe81c
  48. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  49. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  50. #define PLA_CONFIG5 0xe822
  51. #define PLA_PHY_PWR 0xe84c
  52. #define PLA_OOB_CTRL 0xe84f
  53. #define PLA_CPCR 0xe854
  54. #define PLA_MISC_0 0xe858
  55. #define PLA_MISC_1 0xe85a
  56. #define PLA_OCP_GPHY_BASE 0xe86c
  57. #define PLA_TALLYCNT 0xe890
  58. #define PLA_SFF_STS_7 0xe8de
  59. #define PLA_PHYSTATUS 0xe908
  60. #define PLA_BP_BA 0xfc26
  61. #define PLA_BP_0 0xfc28
  62. #define PLA_BP_1 0xfc2a
  63. #define PLA_BP_2 0xfc2c
  64. #define PLA_BP_3 0xfc2e
  65. #define PLA_BP_4 0xfc30
  66. #define PLA_BP_5 0xfc32
  67. #define PLA_BP_6 0xfc34
  68. #define PLA_BP_7 0xfc36
  69. #define PLA_BP_EN 0xfc38
  70. #define USB_USB2PHY 0xb41e
  71. #define USB_SSPHYLINK2 0xb428
  72. #define USB_U2P3_CTRL 0xb460
  73. #define USB_CSR_DUMMY1 0xb464
  74. #define USB_CSR_DUMMY2 0xb466
  75. #define USB_DEV_STAT 0xb808
  76. #define USB_CONNECT_TIMER 0xcbf8
  77. #define USB_MSC_TIMER 0xcbfc
  78. #define USB_BURST_SIZE 0xcfc0
  79. #define USB_FW_FIX_EN1 0xcfcc
  80. #define USB_LPM_CONFIG 0xcfd8
  81. #define USB_USB_CTRL 0xd406
  82. #define USB_PHY_CTRL 0xd408
  83. #define USB_TX_AGG 0xd40a
  84. #define USB_RX_BUF_TH 0xd40c
  85. #define USB_USB_TIMER 0xd428
  86. #define USB_RX_EARLY_TIMEOUT 0xd42c
  87. #define USB_RX_EARLY_SIZE 0xd42e
  88. #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
  89. #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
  90. #define USB_TX_DMA 0xd434
  91. #define USB_TOLERANCE 0xd490
  92. #define USB_LPM_CTRL 0xd41a
  93. #define USB_BMU_RESET 0xd4b0
  94. #define USB_U1U2_TIMER 0xd4da
  95. #define USB_UPS_CTRL 0xd800
  96. #define USB_POWER_CUT 0xd80a
  97. #define USB_MISC_0 0xd81a
  98. #define USB_AFE_CTRL2 0xd824
  99. #define USB_UPS_CFG 0xd842
  100. #define USB_WDT11_CTRL 0xe43c
  101. #define USB_BP_BA PLA_BP_BA
  102. #define USB_BP(n) (0xfc28 + 2 * (n))
  103. #define USB_BP_EN PLA_BP_EN /* RTL8153A */
  104. #define USB_BP2_EN 0xfc48
  105. /* OCP Registers */
  106. #define OCP_ALDPS_CONFIG 0x2010
  107. #define OCP_EEE_CONFIG1 0x2080
  108. #define OCP_EEE_CONFIG2 0x2092
  109. #define OCP_EEE_CONFIG3 0x2094
  110. #define OCP_BASE_MII 0xa400
  111. #define OCP_EEE_AR 0xa41a
  112. #define OCP_EEE_DATA 0xa41c
  113. #define OCP_PHY_STATUS 0xa420
  114. #define OCP_NCTL_CFG 0xa42c
  115. #define OCP_POWER_CFG 0xa430
  116. #define OCP_EEE_CFG 0xa432
  117. #define OCP_SRAM_ADDR 0xa436
  118. #define OCP_SRAM_DATA 0xa438
  119. #define OCP_DOWN_SPEED 0xa442
  120. #define OCP_EEE_ABLE 0xa5c4
  121. #define OCP_EEE_ADV 0xa5d0
  122. #define OCP_EEE_LPABLE 0xa5d2
  123. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  124. #define OCP_ADC_IOFFSET 0xbcfc
  125. #define OCP_ADC_CFG 0xbc06
  126. /* SRAM Register */
  127. #define SRAM_GREEN_CFG 0x8011
  128. #define SRAM_LPF_CFG 0x8012
  129. #define SRAM_10M_AMP1 0x8080
  130. #define SRAM_10M_AMP2 0x8082
  131. #define SRAM_IMPEDANCE 0x8084
  132. /* PLA_RCR */
  133. #define RCR_AAP 0x00000001
  134. #define RCR_APM 0x00000002
  135. #define RCR_AM 0x00000004
  136. #define RCR_AB 0x00000008
  137. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  138. /* PLA_RXFIFO_CTRL0 */
  139. #define RXFIFO_THR1_NORMAL 0x00080002
  140. #define RXFIFO_THR1_OOB 0x01800003
  141. /* PLA_RXFIFO_CTRL1 */
  142. #define RXFIFO_THR2_FULL 0x00000060
  143. #define RXFIFO_THR2_HIGH 0x00000038
  144. #define RXFIFO_THR2_OOB 0x0000004a
  145. #define RXFIFO_THR2_NORMAL 0x00a0
  146. /* PLA_RXFIFO_CTRL2 */
  147. #define RXFIFO_THR3_FULL 0x00000078
  148. #define RXFIFO_THR3_HIGH 0x00000048
  149. #define RXFIFO_THR3_OOB 0x0000005a
  150. #define RXFIFO_THR3_NORMAL 0x0110
  151. /* PLA_TXFIFO_CTRL */
  152. #define TXFIFO_THR_NORMAL 0x00400008
  153. #define TXFIFO_THR_NORMAL2 0x01000008
  154. /* PLA_DMY_REG0 */
  155. #define ECM_ALDPS 0x0002
  156. /* PLA_FMC */
  157. #define FMC_FCR_MCU_EN 0x0001
  158. /* PLA_EEEP_CR */
  159. #define EEEP_CR_EEEP_TX 0x0002
  160. /* PLA_WDT6_CTRL */
  161. #define WDT6_SET_MODE 0x0010
  162. /* PLA_TCR0 */
  163. #define TCR0_TX_EMPTY 0x0800
  164. #define TCR0_AUTO_FIFO 0x0080
  165. /* PLA_TCR1 */
  166. #define VERSION_MASK 0x7cf0
  167. /* PLA_MTPS */
  168. #define MTPS_JUMBO (12 * 1024 / 64)
  169. #define MTPS_DEFAULT (6 * 1024 / 64)
  170. /* PLA_RSTTALLY */
  171. #define TALLY_RESET 0x0001
  172. /* PLA_CR */
  173. #define PLA_CR_RST 0x10
  174. #define PLA_CR_RE 0x08
  175. #define PLA_CR_TE 0x04
  176. /* PLA_BIST_CTRL */
  177. #define BIST_CTRL_SW_RESET (0x10 << 24)
  178. /* PLA_CRWECR */
  179. #define CRWECR_NORAML 0x00
  180. #define CRWECR_CONFIG 0xc0
  181. /* PLA_OOB_CTRL */
  182. #define NOW_IS_OOB 0x80
  183. #define TXFIFO_EMPTY 0x20
  184. #define RXFIFO_EMPTY 0x10
  185. #define LINK_LIST_READY 0x02
  186. #define DIS_MCU_CLROOB 0x01
  187. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  188. /* PLA_PHY_PWR */
  189. #define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
  190. #define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
  191. #define TEST_IO_OFF BIT(4)
  192. /* PLA_MISC_1 */
  193. #define RXDY_GATED_EN 0x0008
  194. /* PLA_SFF_STS_7 */
  195. #define RE_INIT_LL 0x8000
  196. #define MCU_BORW_EN 0x4000
  197. /* PLA_CPCR */
  198. #define CPCR_RX_VLAN 0x0040
  199. /* PLA_CFG_WOL */
  200. #define MAGIC_EN 0x0001
  201. /* PLA_TEREDO_CFG */
  202. #define TEREDO_SEL 0x8000
  203. #define TEREDO_WAKE_MASK 0x7f00
  204. #define TEREDO_RS_EVENT_MASK 0x00fe
  205. #define OOB_TEREDO_EN 0x0001
  206. /* PLA_BDC_CR */
  207. #define ALDPS_PROXY_MODE 0x0001
  208. /* PLA_EFUSE_CMD */
  209. #define EFUSE_READ_CMD BIT(15)
  210. #define EFUSE_DATA_BIT16 BIT(7)
  211. /* PLA_CONFIG34 */
  212. #define LINK_ON_WAKE_EN 0x0010
  213. #define LINK_OFF_WAKE_EN 0x0008
  214. /* PLA_CONFIG5 */
  215. #define BWF_EN 0x0040
  216. #define MWF_EN 0x0020
  217. #define UWF_EN 0x0010
  218. #define LAN_WAKE_EN 0x0002
  219. /* PLA_LED_FEATURE */
  220. #define LED_MODE_MASK 0x0700
  221. /* PLA_PHY_PWR */
  222. #define TX_10M_IDLE_EN 0x0080
  223. #define PFM_PWM_SWITCH 0x0040
  224. /* PLA_MAC_PWR_CTRL */
  225. #define D3_CLK_GATED_EN 0x00004000
  226. #define MCU_CLK_RATIO 0x07010f07
  227. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  228. #define ALDPS_SPDWN_RATIO 0x0f87
  229. /* PLA_MAC_PWR_CTRL2 */
  230. #define EEE_SPDWN_RATIO 0x8007
  231. #define MAC_CLK_SPDWN_EN BIT(15)
  232. /* PLA_MAC_PWR_CTRL3 */
  233. #define PLA_MCU_SPDWN_EN BIT(14)
  234. #define PKT_AVAIL_SPDWN_EN 0x0100
  235. #define SUSPEND_SPDWN_EN 0x0004
  236. #define U1U2_SPDWN_EN 0x0002
  237. #define L1_SPDWN_EN 0x0001
  238. /* PLA_MAC_PWR_CTRL4 */
  239. #define PWRSAVE_SPDWN_EN 0x1000
  240. #define RXDV_SPDWN_EN 0x0800
  241. #define TX10MIDLE_EN 0x0100
  242. #define TP100_SPDWN_EN 0x0020
  243. #define TP500_SPDWN_EN 0x0010
  244. #define TP1000_SPDWN_EN 0x0008
  245. #define EEE_SPDWN_EN 0x0001
  246. /* PLA_GPHY_INTR_IMR */
  247. #define GPHY_STS_MSK 0x0001
  248. #define SPEED_DOWN_MSK 0x0002
  249. #define SPDWN_RXDV_MSK 0x0004
  250. #define SPDWN_LINKCHG_MSK 0x0008
  251. /* PLA_PHYAR */
  252. #define PHYAR_FLAG 0x80000000
  253. /* PLA_EEE_CR */
  254. #define EEE_RX_EN 0x0001
  255. #define EEE_TX_EN 0x0002
  256. /* PLA_BOOT_CTRL */
  257. #define AUTOLOAD_DONE 0x0002
  258. /* PLA_EXTRA_STATUS */
  259. #define U3P3_CHECK_EN BIT(7)
  260. /* USB_USB2PHY */
  261. #define USB2PHY_SUSPEND 0x0001
  262. #define USB2PHY_L1 0x0002
  263. /* USB_SSPHYLINK2 */
  264. #define pwd_dn_scale_mask 0x3ffe
  265. #define pwd_dn_scale(x) ((x) << 1)
  266. /* USB_CSR_DUMMY1 */
  267. #define DYNAMIC_BURST 0x0001
  268. /* USB_CSR_DUMMY2 */
  269. #define EP4_FULL_FC 0x0001
  270. /* USB_DEV_STAT */
  271. #define STAT_SPEED_MASK 0x0006
  272. #define STAT_SPEED_HIGH 0x0000
  273. #define STAT_SPEED_FULL 0x0002
  274. /* USB_FW_FIX_EN1 */
  275. #define FW_IP_RESET_EN BIT(9)
  276. /* USB_LPM_CONFIG */
  277. #define LPM_U1U2_EN BIT(0)
  278. /* USB_TX_AGG */
  279. #define TX_AGG_MAX_THRESHOLD 0x03
  280. /* USB_RX_BUF_TH */
  281. #define RX_THR_SUPPER 0x0c350180
  282. #define RX_THR_HIGH 0x7a120180
  283. #define RX_THR_SLOW 0xffff0180
  284. /* USB_RX_EARLY_TIMEOUT */
  285. #define RX_AUXILIARY_TIMER 1264
  286. /* USB_TX_DMA */
  287. #define TEST_MODE_DISABLE 0x00000001
  288. #define TX_SIZE_ADJUST1 0x00000100
  289. /* USB_BMU_RESET */
  290. #define BMU_RESET_EP_IN 0x01
  291. #define BMU_RESET_EP_OUT 0x02
  292. /* USB_UPS_CTRL */
  293. #define POWER_CUT 0x0100
  294. /* USB_PM_CTRL_STATUS */
  295. #define RESUME_INDICATE 0x0001
  296. /* USB_USB_CTRL */
  297. #define RX_AGG_DISABLE 0x0010
  298. #define RX_ZERO_EN 0x0080
  299. /* USB_U2P3_CTRL */
  300. #define U2P3_ENABLE 0x0001
  301. /* USB_POWER_CUT */
  302. #define PWR_EN 0x0001
  303. #define PHASE2_EN 0x0008
  304. /* USB_MISC_0 */
  305. #define PCUT_STATUS 0x0001
  306. /* USB_RX_EARLY_TIMEOUT */
  307. #define COALESCE_SUPER 85000U
  308. #define COALESCE_HIGH 250000U
  309. #define COALESCE_SLOW 524280U
  310. /* USB_WDT11_CTRL */
  311. #define TIMER11_EN 0x0001
  312. /* USB_LPM_CTRL */
  313. /* bit 4 ~ 5: fifo empty boundary */
  314. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  315. /* bit 2 ~ 3: LMP timer */
  316. #define LPM_TIMER_MASK 0x0c
  317. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  318. #define LPM_TIMER_500US 0x0c /* 500 us */
  319. #define ROK_EXIT_LPM 0x02
  320. /* USB_AFE_CTRL2 */
  321. #define SEN_VAL_MASK 0xf800
  322. #define SEN_VAL_NORMAL 0xa000
  323. #define SEL_RXIDLE 0x0100
  324. /* USB_UPS_CFG */
  325. #define SAW_CNT_1MS_MASK 0x0fff
  326. /* OCP_ALDPS_CONFIG */
  327. #define ENPWRSAVE 0x8000
  328. #define ENPDNPS 0x0200
  329. #define LINKENA 0x0100
  330. #define DIS_SDSAVE 0x0010
  331. /* OCP_PHY_STATUS */
  332. #define PHY_STAT_MASK 0x0007
  333. #define PHY_STAT_LAN_ON 3
  334. #define PHY_STAT_PWRDN 5
  335. /* OCP_NCTL_CFG */
  336. #define PGA_RETURN_EN BIT(1)
  337. /* OCP_POWER_CFG */
  338. #define EEE_CLKDIV_EN 0x8000
  339. #define EN_ALDPS 0x0004
  340. #define EN_10M_PLLOFF 0x0001
  341. /* OCP_EEE_CONFIG1 */
  342. #define RG_TXLPI_MSK_HFDUP 0x8000
  343. #define RG_MATCLR_EN 0x4000
  344. #define EEE_10_CAP 0x2000
  345. #define EEE_NWAY_EN 0x1000
  346. #define TX_QUIET_EN 0x0200
  347. #define RX_QUIET_EN 0x0100
  348. #define sd_rise_time_mask 0x0070
  349. #define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
  350. #define RG_RXLPI_MSK_HFDUP 0x0008
  351. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  352. /* OCP_EEE_CONFIG2 */
  353. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  354. #define RG_DACQUIET_EN 0x0400
  355. #define RG_LDVQUIET_EN 0x0200
  356. #define RG_CKRSEL 0x0020
  357. #define RG_EEEPRG_EN 0x0010
  358. /* OCP_EEE_CONFIG3 */
  359. #define fast_snr_mask 0xff80
  360. #define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
  361. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  362. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  363. /* OCP_EEE_AR */
  364. /* bit[15:14] function */
  365. #define FUN_ADDR 0x0000
  366. #define FUN_DATA 0x4000
  367. /* bit[4:0] device addr */
  368. /* OCP_EEE_CFG */
  369. #define CTAP_SHORT_EN 0x0040
  370. #define EEE10_EN 0x0010
  371. /* OCP_DOWN_SPEED */
  372. #define EN_10M_BGOFF 0x0080
  373. /* OCP_PHY_STATE */
  374. #define TXDIS_STATE 0x01
  375. #define ABD_STATE 0x02
  376. /* OCP_ADC_CFG */
  377. #define CKADSEL_L 0x0100
  378. #define ADC_EN 0x0080
  379. #define EN_EMI_L 0x0040
  380. /* SRAM_GREEN_CFG */
  381. #define GREEN_ETH_EN BIT(15)
  382. #define R_TUNE_EN BIT(11)
  383. /* SRAM_LPF_CFG */
  384. #define LPF_AUTO_TUNE 0x8000
  385. /* SRAM_10M_AMP1 */
  386. #define GDAC_IB_UPALL 0x0008
  387. /* SRAM_10M_AMP2 */
  388. #define AMP_DN 0x0200
  389. /* SRAM_IMPEDANCE */
  390. #define RX_DRIVING_MASK 0x6000
  391. #define RTL8152_MAX_TX 4
  392. #define RTL8152_MAX_RX 10
  393. #define INTBUFSIZE 2
  394. #define CRC_SIZE 4
  395. #define TX_ALIGN 4
  396. #define RX_ALIGN 8
  397. #define INTR_LINK 0x0004
  398. #define RTL8152_REQT_READ 0xc0
  399. #define RTL8152_REQT_WRITE 0x40
  400. #define RTL8152_REQ_GET_REGS 0x05
  401. #define RTL8152_REQ_SET_REGS 0x05
  402. #define BYTE_EN_DWORD 0xff
  403. #define BYTE_EN_WORD 0x33
  404. #define BYTE_EN_BYTE 0x11
  405. #define BYTE_EN_SIX_BYTES 0x3f
  406. #define BYTE_EN_START_MASK 0x0f
  407. #define BYTE_EN_END_MASK 0xf0
  408. #define RTL8152_ETH_FRAME_LEN 1514
  409. #define RTL8152_AGG_BUF_SZ 2048
  410. #define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
  411. #define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
  412. #define RTL8152_TX_TIMEOUT (5 * HZ)
  413. #define MCU_TYPE_PLA 0x0100
  414. #define MCU_TYPE_USB 0x0000
  415. /* The forced speed, 10Mb, 100Mb, gigabit. */
  416. #define SPEED_10 10
  417. #define SPEED_100 100
  418. #define SPEED_1000 1000
  419. #define SPEED_UNKNOWN -1
  420. /* Duplex, half or full. */
  421. #define DUPLEX_HALF 0x00
  422. #define DUPLEX_FULL 0x01
  423. #define DUPLEX_UNKNOWN 0xff
  424. /* Enable or disable autonegotiation. */
  425. #define AUTONEG_DISABLE 0x00
  426. #define AUTONEG_ENABLE 0x01
  427. /* Generic MII registers. */
  428. #define MII_BMCR 0x00 /* Basic mode control register */
  429. #define MII_BMSR 0x01 /* Basic mode status register */
  430. #define MII_PHYSID1 0x02 /* PHYS ID 1 */
  431. #define MII_PHYSID2 0x03 /* PHYS ID 2 */
  432. #define MII_ADVERTISE 0x04 /* Advertisement control reg */
  433. #define MII_LPA 0x05 /* Link partner ability reg */
  434. #define MII_EXPANSION 0x06 /* Expansion register */
  435. #define MII_CTRL1000 0x09 /* 1000BASE-T control */
  436. #define MII_STAT1000 0x0a /* 1000BASE-T status */
  437. #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
  438. #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
  439. #define MII_ESTATUS 0x0f /* Extended Status */
  440. #define MII_DCOUNTER 0x12 /* Disconnect counter */
  441. #define MII_FCSCOUNTER 0x13 /* False carrier counter */
  442. #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
  443. #define MII_RERRCOUNTER 0x15 /* Receive error counter */
  444. #define MII_SREVISION 0x16 /* Silicon revision */
  445. #define MII_RESV1 0x17 /* Reserved... */
  446. #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
  447. #define MII_PHYADDR 0x19 /* PHY address */
  448. #define MII_RESV2 0x1a /* Reserved... */
  449. #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
  450. #define MII_NCONFIG 0x1c /* Network interface config */
  451. #define TIMEOUT_RESOLUTION 50
  452. #define PHY_CONNECT_TIMEOUT 5000
  453. #define USB_BULK_SEND_TIMEOUT 5000
  454. #define USB_BULK_RECV_TIMEOUT 5000
  455. #define R8152_WAIT_TIMEOUT 2000
  456. struct rx_desc {
  457. __le32 opts1;
  458. #define RD_CRC BIT(15)
  459. #define RX_LEN_MASK 0x7fff
  460. __le32 opts2;
  461. #define RD_UDP_CS BIT(23)
  462. #define RD_TCP_CS BIT(22)
  463. #define RD_IPV6_CS BIT(20)
  464. #define RD_IPV4_CS BIT(19)
  465. __le32 opts3;
  466. #define IPF BIT(23) /* IP checksum fail */
  467. #define UDPF BIT(22) /* UDP checksum fail */
  468. #define TCPF BIT(21) /* TCP checksum fail */
  469. #define RX_VLAN_TAG BIT(16)
  470. __le32 opts4;
  471. __le32 opts5;
  472. __le32 opts6;
  473. };
  474. struct tx_desc {
  475. __le32 opts1;
  476. #define TX_FS BIT(31) /* First segment of a packet */
  477. #define TX_LS BIT(30) /* Final segment of a packet */
  478. #define LGSEND BIT(29)
  479. #define GTSENDV4 BIT(28)
  480. #define GTSENDV6 BIT(27)
  481. #define GTTCPHO_SHIFT 18
  482. #define GTTCPHO_MAX 0x7fU
  483. #define TX_LEN_MAX 0x3ffffU
  484. __le32 opts2;
  485. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  486. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  487. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  488. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  489. #define MSS_SHIFT 17
  490. #define MSS_MAX 0x7ffU
  491. #define TCPHO_SHIFT 17
  492. #define TCPHO_MAX 0x7ffU
  493. #define TX_VLAN_TAG BIT(16)
  494. };
  495. enum rtl_version {
  496. RTL_VER_UNKNOWN = 0,
  497. RTL_VER_01,
  498. RTL_VER_02,
  499. RTL_VER_03,
  500. RTL_VER_04,
  501. RTL_VER_05,
  502. RTL_VER_06,
  503. RTL_VER_07,
  504. RTL_VER_08,
  505. RTL_VER_09,
  506. RTL_VER_MAX
  507. };
  508. enum rtl_register_content {
  509. _1000bps = 0x10,
  510. _100bps = 0x08,
  511. _10bps = 0x04,
  512. LINK_STATUS = 0x02,
  513. FULL_DUP = 0x01,
  514. };
  515. struct r8152 {
  516. struct usb_device *udev;
  517. struct usb_interface *intf;
  518. bool supports_gmii;
  519. struct rtl_ops {
  520. void (*init)(struct r8152 *);
  521. int (*enable)(struct r8152 *);
  522. void (*disable)(struct r8152 *);
  523. void (*up)(struct r8152 *);
  524. void (*down)(struct r8152 *);
  525. void (*unload)(struct r8152 *);
  526. } rtl_ops;
  527. u32 coalesce;
  528. u16 ocp_base;
  529. u8 version;
  530. #ifdef CONFIG_DM_ETH
  531. struct ueth_data ueth;
  532. #endif
  533. };
  534. int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  535. u16 size, void *data, u16 type);
  536. int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  537. void *data, u16 type);
  538. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
  539. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  540. u16 size, void *data);
  541. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
  542. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  543. u16 size, void *data);
  544. u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
  545. void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
  546. u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
  547. void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
  548. u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
  549. void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
  550. u16 ocp_reg_read(struct r8152 *tp, u16 addr);
  551. void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
  552. void sram_write(struct r8152 *tp, u16 addr, u16 data);
  553. int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
  554. const u32 mask, bool set, unsigned int timeout);
  555. void r8152b_firmware(struct r8152 *tp);
  556. void r8153_firmware(struct r8152 *tp);
  557. void r8153b_firmware(struct r8152 *tp);
  558. #endif