colibri_imx7.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2018 Toradex AG
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/mx7-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/io.h>
  16. #include <common.h>
  17. #include <dm.h>
  18. #include <dm/platform_data/serial_mxc.h>
  19. #include <fdt_support.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <jffs2/load_kernel.h>
  22. #include <linux/sizes.h>
  23. #include <mmc.h>
  24. #include <miiphy.h>
  25. #include <mtd_node.h>
  26. #include <netdev.h>
  27. #include <power/pmic.h>
  28. #include <power/rn5t567_pmic.h>
  29. #include <usb.h>
  30. #include <usb/ehci-ci.h>
  31. #include "../common/tdx-common.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  34. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  35. #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  36. #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
  37. #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  38. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  39. PAD_CTL_DSE_3P3V_49OHM)
  40. #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  41. #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  42. #define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
  43. int dram_init(void)
  44. {
  45. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  46. return 0;
  47. }
  48. static iomux_v3_cfg_t const uart1_pads[] = {
  49. MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  52. MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  53. };
  54. #ifdef CONFIG_USB_EHCI_MX7
  55. static iomux_v3_cfg_t const usb_cdet_pads[] = {
  56. MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  57. };
  58. #endif
  59. #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  60. static iomux_v3_cfg_t const gpmi_pads[] = {
  61. MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  62. MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  63. MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  64. MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  65. MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66. MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  76. };
  77. static void setup_gpmi_nand(void)
  78. {
  79. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  80. /* NAND_USDHC_BUS_CLK is set in rom */
  81. set_clk_nand();
  82. }
  83. #endif
  84. #ifdef CONFIG_VIDEO_MXS
  85. static iomux_v3_cfg_t const lcd_pads[] = {
  86. MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  87. MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  88. MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  89. MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  90. MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  91. MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  92. MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  93. MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  94. MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  95. MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  96. MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  97. MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  98. MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  99. MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  100. MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  101. MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  102. MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  103. MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  104. MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  105. MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  106. MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  107. MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  108. };
  109. static iomux_v3_cfg_t const backlight_pads[] = {
  110. /* Backlight On */
  111. MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  112. /* Backlight PWM<A> (multiplexed pin) */
  113. MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114. MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  115. };
  116. #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
  117. #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
  118. static int setup_lcd(void)
  119. {
  120. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  121. imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
  122. /* Set BL_ON */
  123. gpio_request(GPIO_BL_ON, "BL_ON");
  124. gpio_direction_output(GPIO_BL_ON, 1);
  125. /* Set PWM<A> to full brightness (assuming inversed polarity) */
  126. gpio_request(GPIO_PWM_A, "PWM<A>");
  127. gpio_direction_output(GPIO_PWM_A, 0);
  128. return 0;
  129. }
  130. #endif
  131. /*
  132. * Backlight off before OS handover
  133. */
  134. void board_preboot_os(void)
  135. {
  136. gpio_direction_output(GPIO_PWM_A, 1);
  137. gpio_direction_output(GPIO_BL_ON, 0);
  138. }
  139. static void setup_iomux_uart(void)
  140. {
  141. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  142. }
  143. #ifdef CONFIG_FEC_MXC
  144. static int setup_fec(void)
  145. {
  146. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  147. = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  148. #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
  149. /*
  150. * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
  151. * and output it on the pin
  152. */
  153. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  154. IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
  155. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
  156. #else
  157. /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
  158. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  159. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
  160. IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
  161. #endif
  162. return set_clk_enet(ENET_50MHZ);
  163. }
  164. #endif
  165. int board_early_init_f(void)
  166. {
  167. setup_iomux_uart();
  168. return 0;
  169. }
  170. int board_init(void)
  171. {
  172. /* address of boot parameters */
  173. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  174. #ifdef CONFIG_FEC_MXC
  175. setup_fec();
  176. #endif
  177. #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  178. setup_gpmi_nand();
  179. #endif
  180. #ifdef CONFIG_VIDEO_MXS
  181. setup_lcd();
  182. #endif
  183. #ifdef CONFIG_USB_EHCI_MX7
  184. imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
  185. gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
  186. #endif
  187. return 0;
  188. }
  189. #ifdef CONFIG_DM_PMIC
  190. int power_init_board(void)
  191. {
  192. struct udevice *dev;
  193. int reg, ver;
  194. int ret;
  195. ret = pmic_get("rn5t567@33", &dev);
  196. if (ret)
  197. return ret;
  198. ver = pmic_reg_read(dev, RN5T567_LSIVER);
  199. reg = pmic_reg_read(dev, RN5T567_OTPVER);
  200. printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
  201. /* set judge and press timer of N_OE to minimal values */
  202. pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
  203. /* configure sleep slot for 3.3V Ethernet */
  204. reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
  205. reg = (reg & 0xf0) | reg >> 4;
  206. pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
  207. /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
  208. pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
  209. /* configure sleep slot for ARM rail */
  210. reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
  211. reg = (reg & 0xf0) | reg >> 4;
  212. pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
  213. /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
  214. pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
  215. return 0;
  216. }
  217. void reset_cpu(ulong addr)
  218. {
  219. struct udevice *dev;
  220. pmic_get("rn5t567@33", &dev);
  221. /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
  222. pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
  223. pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
  224. /*
  225. * Re-power factor detection on PMIC side is not instant. 1ms
  226. * proved to be enough time until reset takes effect.
  227. */
  228. mdelay(1);
  229. }
  230. #endif
  231. int checkboard(void)
  232. {
  233. printf("Model: Toradex Colibri iMX7%c\n",
  234. is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
  235. return 0;
  236. }
  237. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  238. int ft_board_setup(void *blob, bd_t *bd)
  239. {
  240. #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
  241. int up;
  242. up = arch_auxiliary_core_check_up(0);
  243. if (up) {
  244. int ret;
  245. int areas = 1;
  246. u64 start[2], size[2];
  247. /*
  248. * Reserve 1MB of memory for M4 (1MiB is also the minimum
  249. * alignment for Linux due to MMU section size restrictions).
  250. */
  251. start[0] = gd->bd->bi_dram[0].start;
  252. size[0] = SZ_256M - SZ_1M;
  253. /* If needed, create a second entry for memory beyond 256M */
  254. if (gd->bd->bi_dram[0].size > SZ_256M) {
  255. start[1] = gd->bd->bi_dram[0].start + SZ_256M;
  256. size[1] = gd->bd->bi_dram[0].size - SZ_256M;
  257. areas = 2;
  258. }
  259. ret = fdt_set_usable_memory(blob, start, size, areas);
  260. if (ret) {
  261. eprintf("Cannot set usable memory\n");
  262. return ret;
  263. }
  264. } else {
  265. int off;
  266. off = fdt_node_offset_by_compatible(blob, -1,
  267. "fsl,imx7d-rpmsg");
  268. if (off > 0)
  269. fdt_status_disabled(blob, off);
  270. }
  271. #endif
  272. #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
  273. static const struct node_info nodes[] = {
  274. { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  275. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
  276. };
  277. /* Update partition nodes using info from mtdparts env var */
  278. puts(" Updating MTD partitions...\n");
  279. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  280. #endif
  281. return ft_common_board_setup(blob, bd);
  282. }
  283. #endif
  284. #ifdef CONFIG_USB_EHCI_MX7
  285. static iomux_v3_cfg_t const usb_otg2_pads[] = {
  286. MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  287. };
  288. int board_ehci_hcd_init(int port)
  289. {
  290. switch (port) {
  291. case 0:
  292. break;
  293. case 1:
  294. if (is_cpu_type(MXC_CPU_MX7S))
  295. return -ENODEV;
  296. imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  297. ARRAY_SIZE(usb_otg2_pads));
  298. break;
  299. default:
  300. return -EINVAL;
  301. }
  302. return 0;
  303. }
  304. int board_usb_phy_mode(int port)
  305. {
  306. switch (port) {
  307. case 0:
  308. if (gpio_get_value(USB_CDET_GPIO))
  309. return USB_INIT_DEVICE;
  310. else
  311. return USB_INIT_HOST;
  312. case 1:
  313. default:
  314. return USB_INIT_HOST;
  315. }
  316. }
  317. #endif