pm9263.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <linux/sizes.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/at91sam9_smc.h>
  15. #include <asm/arch/at91_common.h>
  16. #include <asm/arch/at91_rstc.h>
  17. #include <asm/arch/at91_matrix.h>
  18. #include <asm/arch/clk.h>
  19. #include <asm/arch/gpio.h>
  20. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  21. #include <net.h>
  22. #endif
  23. #include <netdev.h>
  24. #include <asm/mach-types.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /* ------------------------------------------------------------------------- */
  27. /*
  28. * Miscelaneous platform dependent initialisations
  29. */
  30. #ifdef CONFIG_CMD_NAND
  31. static void pm9263_nand_hw_init(void)
  32. {
  33. unsigned long csa;
  34. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
  35. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36. /* Enable CS3 */
  37. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  38. writel(csa, &matrix->csa[0]);
  39. /* Configure SMC CS3 for NAND/SmartMedia */
  40. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  41. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  42. &smc->cs[3].setup);
  43. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  44. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  45. &smc->cs[3].pulse);
  46. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  47. &smc->cs[3].cycle);
  48. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  49. AT91_SMC_MODE_EXNW_DISABLE |
  50. #ifdef CONFIG_SYS_NAND_DBW_16
  51. AT91_SMC_MODE_DBW_16 |
  52. #else /* CONFIG_SYS_NAND_DBW_8 */
  53. AT91_SMC_MODE_DBW_8 |
  54. #endif
  55. AT91_SMC_MODE_TDF_CYCLE(2),
  56. &smc->cs[3].mode);
  57. /* Configure RDY/BSY */
  58. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  59. /* Enable NandFlash */
  60. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  61. }
  62. #endif
  63. #ifdef CONFIG_MACB
  64. static void pm9263_macb_hw_init(void)
  65. {
  66. /*
  67. * PB27 enables the 50MHz oscillator for Ethernet PHY
  68. * 1 - enable
  69. * 0 - disable
  70. */
  71. at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
  72. at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
  73. at91_periph_clk_enable(ATMEL_ID_EMAC);
  74. /*
  75. * Disable pull-up on:
  76. * RXDV (PC25) => PHY normal mode (not Test mode)
  77. * ERX0 (PE25) => PHY ADDR0
  78. * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  79. *
  80. * PHY has internal pull-down
  81. */
  82. at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
  83. at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
  84. at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
  85. /* Re-enable pull-up */
  86. at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
  87. at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
  88. at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
  89. at91_macb_hw_init();
  90. }
  91. #endif
  92. #ifdef CONFIG_LCD
  93. #ifdef CONFIG_LCD_IN_PSRAM
  94. #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
  95. #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
  96. /* Initialize the PSRAM memory */
  97. static int pm9263_lcd_hw_psram_init(void)
  98. {
  99. unsigned long csa;
  100. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
  101. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  102. /* Enable CS3 3.3v, no pull-ups */
  103. csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
  104. AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
  105. writel(csa, &matrix->csa[1]);
  106. /* Configure SMC1 CS0 for PSRAM - 16-bit */
  107. writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
  108. AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
  109. &smc->cs[0].setup);
  110. writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
  111. AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
  112. &smc->cs[0].pulse);
  113. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  114. &smc->cs[0].cycle);
  115. writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
  116. &smc->cs[0].mode);
  117. /* setup PB29 as output */
  118. at91_set_pio_output(PSRAM_CRE_PIN, 1);
  119. at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
  120. /* PSRAM: write BCR */
  121. readw(PSRAM_CTRL_REG);
  122. readw(PSRAM_CTRL_REG);
  123. writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  124. writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
  125. /* write RCR of the PSRAM */
  126. readw(PSRAM_CTRL_REG);
  127. readw(PSRAM_CTRL_REG);
  128. writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  129. /* set RCR; 0x10-async mode,0x90-page mode */
  130. writew(0x90, PSRAM_CTRL_REG);
  131. /*
  132. * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
  133. * MT45W2M16B - CRE must be 0
  134. * MT45W2M16A - CRE must be 1
  135. */
  136. writew(0x1234, PHYS_PSRAM);
  137. writew(0x5678, PHYS_PSRAM + 2);
  138. /* test if the chip is MT45W2M16B */
  139. if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
  140. /* try with CRE=1 (MT45W2M16A) */
  141. at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
  142. /* write RCR of the PSRAM */
  143. readw(PSRAM_CTRL_REG);
  144. readw(PSRAM_CTRL_REG);
  145. writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  146. /* set RCR;0x10-async mode,0x90-page mode */
  147. writew(0x90, PSRAM_CTRL_REG);
  148. writew(0x1234, PHYS_PSRAM);
  149. writew(0x5678, PHYS_PSRAM+2);
  150. if ((readw(PHYS_PSRAM) != 0x1234)
  151. || (readw(PHYS_PSRAM + 2) != 0x5678))
  152. return 1;
  153. }
  154. /* Bus matrix */
  155. writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
  156. writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
  157. return 0;
  158. }
  159. #endif
  160. static void pm9263_lcd_hw_init(void)
  161. {
  162. /* Power Control */
  163. at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
  164. at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
  165. #ifdef CONFIG_LCD_IN_PSRAM
  166. /* initialize te PSRAM */
  167. int stat = pm9263_lcd_hw_psram_init();
  168. gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
  169. #else
  170. gd->fb_base = ATMEL_BASE_SRAM0;
  171. #endif
  172. }
  173. #endif /* CONFIG_LCD */
  174. int board_early_init_f(void)
  175. {
  176. return 0;
  177. }
  178. int board_init(void)
  179. {
  180. /* arch number of AT91SAM9263EK-Board */
  181. gd->bd->bi_arch_number = MACH_TYPE_PM9263;
  182. /* adress of boot parameters */
  183. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  184. #ifdef CONFIG_CMD_NAND
  185. pm9263_nand_hw_init();
  186. #endif
  187. #ifdef CONFIG_MACB
  188. pm9263_macb_hw_init();
  189. #endif
  190. #ifdef CONFIG_USB_OHCI_NEW
  191. at91_uhp_hw_init();
  192. #endif
  193. #ifdef CONFIG_LCD
  194. pm9263_lcd_hw_init();
  195. #endif
  196. return 0;
  197. }
  198. int dram_init(void)
  199. {
  200. /* dram_init must store complete ramsize in gd->ram_size */
  201. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  202. PHYS_SDRAM_SIZE);
  203. return 0;
  204. }
  205. int dram_init_banksize(void)
  206. {
  207. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  208. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  209. return 0;
  210. }
  211. #ifdef CONFIG_RESET_PHY_R
  212. void reset_phy(void)
  213. {
  214. }
  215. #endif
  216. int board_eth_init(bd_t *bis)
  217. {
  218. int rc = 0;
  219. #ifdef CONFIG_MACB
  220. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
  221. #endif
  222. return rc;
  223. }
  224. #ifdef CONFIG_DISPLAY_BOARDINFO
  225. int checkboard (void)
  226. {
  227. char *ss;
  228. printf ("Board : Ronetix PM9263\n");
  229. switch (gd->fb_base) {
  230. case PHYS_PSRAM:
  231. ss = "(PSRAM)";
  232. break;
  233. case ATMEL_BASE_SRAM0:
  234. ss = "(Internal SRAM)";
  235. break;
  236. default:
  237. ss = "";
  238. break;
  239. }
  240. printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
  241. printf ("\n");
  242. return 0;
  243. }
  244. #endif