pm9261.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  7. * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <vsprintf.h>
  12. #include <linux/sizes.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/at91sam9_smc.h>
  16. #include <asm/arch/at91_common.h>
  17. #include <asm/arch/at91_rstc.h>
  18. #include <asm/arch/at91_matrix.h>
  19. #include <asm/arch/clk.h>
  20. #include <asm/arch/gpio.h>
  21. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  22. #include <net.h>
  23. #endif
  24. #include <netdev.h>
  25. #include <asm/mach-types.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* ------------------------------------------------------------------------- */
  28. /*
  29. * Miscelaneous platform dependent initialisations
  30. */
  31. #ifdef CONFIG_CMD_NAND
  32. static void pm9261_nand_hw_init(void)
  33. {
  34. unsigned long csa;
  35. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37. /* Enable CS3 */
  38. csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  39. writel(csa, &matrix->csa);
  40. /* Configure SMC CS3 for NAND/SmartMedia */
  41. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  42. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  43. &smc->cs[3].setup);
  44. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  45. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  46. &smc->cs[3].pulse);
  47. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  48. &smc->cs[3].cycle);
  49. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  50. AT91_SMC_MODE_EXNW_DISABLE |
  51. #ifdef CONFIG_SYS_NAND_DBW_16
  52. AT91_SMC_MODE_DBW_16 |
  53. #else /* CONFIG_SYS_NAND_DBW_8 */
  54. AT91_SMC_MODE_DBW_8 |
  55. #endif
  56. AT91_SMC_MODE_TDF_CYCLE(2),
  57. &smc->cs[3].mode);
  58. at91_periph_clk_enable(ATMEL_ID_PIOA);
  59. at91_periph_clk_enable(ATMEL_ID_PIOC);
  60. /* Configure RDY/BSY */
  61. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  62. /* Enable NandFlash */
  63. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  64. at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
  65. at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
  66. }
  67. #endif
  68. #ifdef CONFIG_DRIVER_DM9000
  69. static void pm9261_dm9000_hw_init(void)
  70. {
  71. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  72. /* Configure SMC CS2 for DM9000 */
  73. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  74. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  75. &smc->cs[2].setup);
  76. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
  77. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
  78. &smc->cs[2].pulse);
  79. writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
  80. &smc->cs[2].cycle);
  81. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  82. AT91_SMC_MODE_EXNW_DISABLE |
  83. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  84. AT91_SMC_MODE_TDF_CYCLE(1),
  85. &smc->cs[2].mode);
  86. /* Configure Interrupt pin as input, no pull-up */
  87. at91_periph_clk_enable(ATMEL_ID_PIOA);
  88. at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
  89. }
  90. #endif
  91. int board_early_init_f(void)
  92. {
  93. return 0;
  94. }
  95. int board_init(void)
  96. {
  97. /* arch number of PM9261-Board */
  98. gd->bd->bi_arch_number = MACH_TYPE_PM9261;
  99. /* adress of boot parameters */
  100. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  101. #ifdef CONFIG_CMD_NAND
  102. pm9261_nand_hw_init();
  103. #endif
  104. #ifdef CONFIG_DRIVER_DM9000
  105. pm9261_dm9000_hw_init();
  106. #endif
  107. return 0;
  108. }
  109. #ifdef CONFIG_DRIVER_DM9000
  110. int board_eth_init(bd_t *bis)
  111. {
  112. return dm9000_initialize(bis);
  113. }
  114. #endif
  115. int dram_init(void)
  116. {
  117. /* dram_init must store complete ramsize in gd->ram_size */
  118. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  119. PHYS_SDRAM_SIZE);
  120. return 0;
  121. }
  122. int dram_init_banksize(void)
  123. {
  124. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  125. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  126. return 0;
  127. }
  128. #ifdef CONFIG_RESET_PHY_R
  129. void reset_phy(void)
  130. {
  131. #ifdef CONFIG_DRIVER_DM9000
  132. /*
  133. * Initialize ethernet HW addr prior to starting Linux,
  134. * needed for nfsroot
  135. */
  136. eth_init();
  137. #endif
  138. }
  139. #endif
  140. #ifdef CONFIG_DISPLAY_BOARDINFO
  141. int checkboard (void)
  142. {
  143. char buf[32];
  144. printf ("Board : Ronetix PM9261\n");
  145. printf ("Crystal frequency: %8s MHz\n",
  146. strmhz(buf, get_main_clk_rate()));
  147. printf ("CPU clock : %8s MHz\n",
  148. strmhz(buf, get_cpu_clk_rate()));
  149. printf ("Master clock : %8s MHz\n",
  150. strmhz(buf, get_mck_clk_rate()));
  151. return 0;
  152. }
  153. #endif