picosam9g45.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
  4. * (C) Copyright 2015 Inter Act B.V.
  5. *
  6. * Based on:
  7. * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
  8. * (C) Copyright 2007-2008
  9. * Stelian Pop <stelian@popies.net>
  10. * Lead Tech Design <www.leadtechdesign.com>
  11. */
  12. #include <common.h>
  13. #include <init.h>
  14. #include <vsprintf.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clk.h>
  17. #include <asm/arch/at91sam9g45_matrix.h>
  18. #include <asm/arch/at91sam9_smc.h>
  19. #include <asm/arch/at91_common.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/clk.h>
  22. #include <lcd.h>
  23. #include <linux/mtd/rawnand.h>
  24. #include <atmel_lcdc.h>
  25. #include <atmel_mci.h>
  26. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  27. #include <net.h>
  28. #endif
  29. #include <netdev.h>
  30. #include <asm/mach-types.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /* ------------------------------------------------------------------------- */
  33. /*
  34. * Miscelaneous platform dependent initialisations
  35. */
  36. #if defined(CONFIG_SPL_BUILD)
  37. #include <spl.h>
  38. void at91_spl_board_init(void)
  39. {
  40. #ifdef CONFIG_SYS_USE_MMC
  41. at91_mci_hw_init();
  42. #endif
  43. }
  44. #include <asm/arch/atmel_mpddrc.h>
  45. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  46. {
  47. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  48. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  49. ATMEL_MPDDRC_CR_NR_ROW_14 |
  50. ATMEL_MPDDRC_CR_DQMS_SHARED |
  51. ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  52. ddr2->rtr = 0x24b;
  53. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  54. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  55. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  56. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  57. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  58. 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  59. 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  60. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  61. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  62. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  63. 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  64. 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  65. ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  66. 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  67. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  68. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  69. }
  70. void mem_init(void)
  71. {
  72. struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  73. struct atmel_mpddrc_config ddr2;
  74. unsigned long csa;
  75. ddr2_conf(&ddr2);
  76. at91_system_clk_enable(AT91_PMC_DDR);
  77. /* Chip select 1 is for DDR2/SDRAM */
  78. csa = readl(&mat->ebicsa);
  79. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  80. csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
  81. writel(csa, &mat->ebicsa);
  82. /* DDRAM2 Controller initialize */
  83. ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
  84. ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
  85. }
  86. #endif
  87. #ifdef CONFIG_CMD_USB
  88. static void picosam9g45_usb_hw_init(void)
  89. {
  90. at91_periph_clk_enable(ATMEL_ID_PIODE);
  91. at91_set_gpio_output(AT91_PIN_PD1, 0);
  92. at91_set_gpio_output(AT91_PIN_PD3, 0);
  93. }
  94. #endif
  95. #ifdef CONFIG_MACB
  96. static void picosam9g45_macb_hw_init(void)
  97. {
  98. struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  99. at91_periph_clk_enable(ATMEL_ID_EMAC);
  100. /*
  101. * Disable pull-up on:
  102. * RXDV (PA15) => PHY normal mode (not Test mode)
  103. * ERX0 (PA12) => PHY ADDR0
  104. * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  105. *
  106. * PHY has internal pull-down
  107. */
  108. writel(pin_to_mask(AT91_PIN_PA15) |
  109. pin_to_mask(AT91_PIN_PA12) |
  110. pin_to_mask(AT91_PIN_PA13),
  111. &pioa->pudr);
  112. at91_phy_reset();
  113. /* Re-enable pull-up */
  114. writel(pin_to_mask(AT91_PIN_PA15) |
  115. pin_to_mask(AT91_PIN_PA12) |
  116. pin_to_mask(AT91_PIN_PA13),
  117. &pioa->puer);
  118. /* And the pins. */
  119. at91_macb_hw_init();
  120. }
  121. #endif
  122. #ifdef CONFIG_LCD
  123. vidinfo_t panel_info = {
  124. .vl_col = 480,
  125. .vl_row = 272,
  126. .vl_clk = 9000000,
  127. .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
  128. ATMEL_LCDC_INVFRAME_NORMAL,
  129. .vl_bpix = 3,
  130. .vl_tft = 1,
  131. .vl_hsync_len = 45,
  132. .vl_left_margin = 1,
  133. .vl_right_margin = 1,
  134. .vl_vsync_len = 1,
  135. .vl_upper_margin = 40,
  136. .vl_lower_margin = 1,
  137. .mmio = ATMEL_BASE_LCDC,
  138. };
  139. void lcd_enable(void)
  140. {
  141. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  142. }
  143. void lcd_disable(void)
  144. {
  145. at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
  146. }
  147. static void picosam9g45_lcd_hw_init(void)
  148. {
  149. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  150. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  151. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  152. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  153. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  154. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  155. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  156. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  157. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  158. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  159. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  160. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  161. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  162. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  163. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  164. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  165. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  166. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  167. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  168. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  169. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  170. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  171. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  172. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  173. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  174. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  175. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  176. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  177. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  178. at91_periph_clk_enable(ATMEL_ID_LCDC);
  179. gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
  180. }
  181. #ifdef CONFIG_LCD_INFO
  182. #include <nand.h>
  183. #include <version.h>
  184. void lcd_show_board_info(void)
  185. {
  186. ulong dram_size;
  187. int i;
  188. char temp[32];
  189. lcd_printf("%s\n", U_BOOT_VERSION);
  190. lcd_printf("(C) 2015 Inter Act B.V.\n");
  191. lcd_printf("support@interact.nl\n");
  192. lcd_printf("%s CPU at %s MHz\n",
  193. ATMEL_CPU_NAME,
  194. strmhz(temp, get_cpu_clk_rate()));
  195. dram_size = 0;
  196. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  197. dram_size += gd->bd->bi_dram[i].size;
  198. lcd_printf(" %ld MB SDRAM\n", dram_size >> 20);
  199. }
  200. #endif /* CONFIG_LCD_INFO */
  201. #endif
  202. #ifdef CONFIG_GENERIC_ATMEL_MCI
  203. int board_mmc_init(bd_t *bis)
  204. {
  205. at91_mci_hw_init();
  206. return atmel_mci_init((void *)ATMEL_BASE_MCI0);
  207. }
  208. #endif
  209. int board_early_init_f(void)
  210. {
  211. at91_seriald_hw_init();
  212. return 0;
  213. }
  214. int board_init(void)
  215. {
  216. gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
  217. /* adress of boot parameters */
  218. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  219. #ifdef CONFIG_CMD_USB
  220. picosam9g45_usb_hw_init();
  221. #endif
  222. #ifdef CONFIG_ATMEL_SPI
  223. at91_spi0_hw_init(1 << 4);
  224. #endif
  225. #ifdef CONFIG_MACB
  226. picosam9g45_macb_hw_init();
  227. #endif
  228. #ifdef CONFIG_LCD
  229. picosam9g45_lcd_hw_init();
  230. #endif
  231. return 0;
  232. }
  233. int dram_init(void)
  234. {
  235. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
  236. + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  237. return 0;
  238. }
  239. int dram_init_banksize(void)
  240. {
  241. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  242. gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
  243. PHYS_SDRAM_1_SIZE);
  244. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  245. gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
  246. PHYS_SDRAM_2_SIZE);
  247. return 0;
  248. }
  249. #ifdef CONFIG_RESET_PHY_R
  250. void reset_phy(void)
  251. {
  252. }
  253. #endif
  254. int board_eth_init(bd_t *bis)
  255. {
  256. int rc = 0;
  257. #ifdef CONFIG_MACB
  258. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  259. #endif
  260. return rc;
  261. }
  262. /* SPI chip select control */
  263. #ifdef CONFIG_ATMEL_SPI
  264. #include <spi.h>
  265. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  266. {
  267. return bus == 0 && cs < 2;
  268. }
  269. void spi_cs_activate(struct spi_slave *slave)
  270. {
  271. switch (slave->cs) {
  272. case 1:
  273. at91_set_gpio_output(AT91_PIN_PB18, 0);
  274. break;
  275. case 0:
  276. default:
  277. at91_set_gpio_output(AT91_PIN_PB3, 0);
  278. break;
  279. }
  280. }
  281. void spi_cs_deactivate(struct spi_slave *slave)
  282. {
  283. switch (slave->cs) {
  284. case 1:
  285. at91_set_gpio_output(AT91_PIN_PB18, 1);
  286. break;
  287. case 0:
  288. default:
  289. at91_set_gpio_output(AT91_PIN_PB3, 1);
  290. break;
  291. }
  292. }
  293. #endif /* CONFIG_ATMEL_SPI */