wb45n.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. */
  4. #include <common.h>
  5. #include <init.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/at91sam9x5_matrix.h>
  8. #include <asm/arch/at91sam9_smc.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_rstc.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/gpio.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* ------------------------------------------------------------------------- */
  17. /*
  18. * Miscelaneous platform dependent initialisations
  19. */
  20. static void wb45n_nand_hw_init(void)
  21. {
  22. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  23. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  24. unsigned long csa;
  25. csa = readl(&matrix->ebicsa);
  26. /* Enable CS3 */
  27. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  28. /* NAND flash on D0 */
  29. csa &= ~AT91_MATRIX_NFD0_ON_D16;
  30. writel(csa, &matrix->ebicsa);
  31. /* Configure SMC CS3 for NAND/SmartMedia */
  32. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  33. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  34. &smc->cs[3].setup);
  35. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  36. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  37. &smc->cs[3].pulse);
  38. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
  39. &smc->cs[3].cycle);
  40. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  41. AT91_SMC_MODE_EXNW_DISABLE |
  42. AT91_SMC_MODE_DBW_8 |
  43. AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
  44. at91_periph_clk_enable(ATMEL_ID_PIOCD);
  45. /* Configure RDY/BSY */
  46. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  47. /* Enable NandFlash */
  48. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  49. /* Disable Flash Write Protect Line */
  50. at91_set_gpio_output(AT91_PIN_PD10, 1);
  51. at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  52. at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  53. at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
  54. at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
  55. }
  56. static void wb45n_gpio_hw_init(void)
  57. {
  58. /* Configure wifi gpio CHIP_PWD_L */
  59. at91_set_gpio_output(AT91_PIN_PA28, 0);
  60. /* Setup USB pins */
  61. at91_set_gpio_input(AT91_PIN_PB11, 0);
  62. at91_set_gpio_output(AT91_PIN_PB12, 0);
  63. /* IRQ pin, pullup, deglitch */
  64. at91_set_gpio_input(AT91_PIN_PB18, 1);
  65. at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
  66. }
  67. int board_eth_init(bd_t *bis)
  68. {
  69. int rc = 0;
  70. if (has_emac0())
  71. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
  72. return rc;
  73. }
  74. int board_early_init_f(void)
  75. {
  76. at91_seriald_hw_init();
  77. return 0;
  78. }
  79. int board_init(void)
  80. {
  81. /* address of boot parameters */
  82. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  83. wb45n_gpio_hw_init();
  84. wb45n_nand_hw_init();
  85. at91_macb_hw_init();
  86. return 0;
  87. }
  88. int dram_init(void)
  89. {
  90. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  91. CONFIG_SYS_SDRAM_SIZE);
  92. return 0;
  93. }
  94. #if defined(CONFIG_SPL_BUILD)
  95. #include <spl.h>
  96. #include <nand.h>
  97. void at91_spl_board_init(void)
  98. {
  99. /* Setup GPIO first */
  100. wb45n_gpio_hw_init();
  101. /* Bring up NAND */
  102. wb45n_nand_hw_init();
  103. }
  104. void matrix_init(void)
  105. {
  106. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  107. unsigned long csa;
  108. csa = readl(&matrix->ebicsa);
  109. /* Pull ups on D0 - D16 */
  110. csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  111. csa |= AT91_MATRIX_EBI_DBPD_OFF;
  112. /* Normal drive strength */
  113. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  114. /* Multi-port off */
  115. csa &= ~AT91_MATRIX_MP_ON;
  116. writel(csa, &matrix->ebicsa);
  117. }
  118. #include <asm/arch/atmel_mpddrc.h>
  119. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  120. {
  121. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
  122. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  123. ATMEL_MPDDRC_CR_NR_ROW_13 |
  124. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  125. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  126. ATMEL_MPDDRC_CR_DQMS_SHARED);
  127. ddr2->rtr = 0x411;
  128. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  129. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  130. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  131. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  132. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  133. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  134. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  135. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  136. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  137. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  138. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  139. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  140. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  141. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  142. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  143. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  144. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  145. }
  146. void mem_init(void)
  147. {
  148. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  149. struct atmel_mpddrc_config ddr2;
  150. unsigned long csa;
  151. ddr2_conf(&ddr2);
  152. /* enable DDR2 clock */
  153. at91_system_clk_enable(AT91_PMC_DDR);
  154. /* Chip select 1 is for DDR2/SDRAM */
  155. csa = readl(&matrix->ebicsa);
  156. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  157. writel(csa, &matrix->ebicsa);
  158. /* DDRAM2 Controller initialize */
  159. ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
  160. }
  161. #endif