ids8313.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (c) 2011 IDS GmbH, Germany
  8. * ids8313.c - ids8313 board support.
  9. *
  10. * Sergej Stepanov <ste@ids.de>
  11. * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
  12. */
  13. #include <common.h>
  14. #include <fdt_support.h>
  15. #include <init.h>
  16. #include <mpc83xx.h>
  17. #include <spi.h>
  18. #include <linux/libfdt.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /** CPLD contains the info about:
  21. * - board type: *pCpld & 0xF0
  22. * - hw-revision: *pCpld & 0x0F
  23. * - cpld-revision: *pCpld+1
  24. */
  25. int checkboard(void)
  26. {
  27. char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
  28. u8 u8Vers = readb(pcpld);
  29. u8 u8Revs = readb(pcpld + 1);
  30. printf("Board: ");
  31. switch (u8Vers & 0xF0) {
  32. case '\x40':
  33. printf("CU73X");
  34. break;
  35. case '\x50':
  36. printf("CC73X");
  37. break;
  38. default:
  39. printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
  40. return 0;
  41. }
  42. printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
  43. u8Vers & 0x0F, u8Revs & 0xFF);
  44. return 0;
  45. }
  46. /*
  47. * fixed sdram init
  48. */
  49. int fixed_sdram(unsigned long config)
  50. {
  51. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  52. u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  53. #ifndef CONFIG_SYS_RAMBOOT
  54. u32 msize_log2 = __ilog2(msize);
  55. out_be32(&im->sysconf.ddrlaw[0].bar,
  56. (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
  57. out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
  58. out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  59. sync();
  60. /*
  61. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  62. * or the DDR2 controller may fail to initialize correctly.
  63. */
  64. udelay(50000);
  65. out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
  66. out_be32(&im->ddr.cs_config[0], config);
  67. /* currently we use only one CS, so disable the other banks */
  68. out_be32(&im->ddr.cs_config[1], 0);
  69. out_be32(&im->ddr.cs_config[2], 0);
  70. out_be32(&im->ddr.cs_config[3], 0);
  71. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  72. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  73. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  74. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  75. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
  76. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
  77. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  78. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
  79. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  80. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  81. sync();
  82. udelay(300);
  83. /* enable DDR controller */
  84. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  85. /* now check the real size */
  86. disable_addr_trans();
  87. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  88. enable_addr_trans();
  89. #endif
  90. return msize;
  91. }
  92. static int setup_sdram(void)
  93. {
  94. u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  95. long int size_01, size_02;
  96. size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  97. size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
  98. if (size_01 > size_02)
  99. msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  100. else
  101. msize = size_02;
  102. return msize;
  103. }
  104. int dram_init(void)
  105. {
  106. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  107. fsl_lbc_t *lbc = &im->im_lbc;
  108. u32 msize = 0;
  109. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  110. return -ENXIO;
  111. msize = setup_sdram();
  112. out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
  113. out_be32(&lbc->mrtpr, 0x20000000);
  114. sync();
  115. gd->ram_size = msize;
  116. return 0;
  117. }
  118. #if defined(CONFIG_OF_BOARD_SETUP)
  119. int ft_board_setup(void *blob, bd_t *bd)
  120. {
  121. ft_cpu_setup(blob, bd);
  122. return 0;
  123. }
  124. #endif
  125. /* gpio mask for spi_cs */
  126. #define IDSCPLD_SPI_CS_MASK 0x00000001
  127. /* spi_cs multiplexed through cpld */
  128. #define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
  129. #if defined(CONFIG_MISC_INIT_R)
  130. /* srp umcr mask for rts */
  131. #define IDSUMCR_RTS_MASK 0x04
  132. int misc_init_r(void)
  133. {
  134. /*srp*/
  135. duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
  136. duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
  137. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  138. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  139. /* deactivate spi_cs channels */
  140. out_8(spi_base, 0);
  141. /* deactivate the spi_cs */
  142. setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
  143. /*srp - deactivate rts*/
  144. out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
  145. out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
  146. gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
  147. return 0;
  148. }
  149. #endif
  150. #ifdef CONFIG_MPC8XXX_SPI
  151. /*
  152. * The following are used to control the SPI chip selects
  153. */
  154. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  155. {
  156. return bus == 0 && ((cs >= 0) && (cs <= 2));
  157. }
  158. void spi_cs_activate(struct spi_slave *slave)
  159. {
  160. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  161. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  162. /* select the spi_cs channel */
  163. out_8(spi_base, 1 << slave->cs);
  164. /* activate the spi_cs */
  165. clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  166. }
  167. void spi_cs_deactivate(struct spi_slave *slave)
  168. {
  169. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  170. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  171. /* select the spi_cs channel */
  172. out_8(spi_base, 1 << slave->cs);
  173. /* deactivate the spi_cs */
  174. setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  175. }
  176. #endif