mx53ard.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/iomux-mx53.h>
  13. #include <linux/errno.h>
  14. #include <netdev.h>
  15. #include <mmc.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <asm/gpio.h>
  18. #define ETHERNET_INT IMX_GPIO_NR(2, 31)
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int dram_init(void)
  21. {
  22. u32 size1, size2;
  23. size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  24. size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  25. gd->ram_size = size1 + size2;
  26. return 0;
  27. }
  28. int dram_init_banksize(void)
  29. {
  30. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  31. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  32. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  33. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  34. return 0;
  35. }
  36. #ifdef CONFIG_NAND_MXC
  37. static void setup_iomux_nand(void)
  38. {
  39. static const iomux_v3_cfg_t nand_pads[] = {
  40. NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  41. PAD_CTL_DSE_HIGH),
  42. NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
  43. PAD_CTL_DSE_HIGH),
  44. NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  45. PAD_CTL_PUS_100K_UP),
  46. NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  47. PAD_CTL_DSE_HIGH),
  48. NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  49. PAD_CTL_DSE_HIGH),
  50. NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  51. PAD_CTL_PUS_100K_UP),
  52. NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  53. PAD_CTL_DSE_HIGH),
  54. NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  55. PAD_CTL_DSE_HIGH),
  56. NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  57. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  58. NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  59. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  60. NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  61. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  62. NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  63. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  64. NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  65. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  66. NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  67. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  68. NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  69. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  70. NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
  71. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  72. };
  73. u32 i, reg;
  74. reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
  75. reg &= ~M4IF_GENP_WEIM_MM_MASK;
  76. __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
  77. for (i = 0x4; i < 0x94; i += 0x18) {
  78. reg = __raw_readl(WEIM_BASE_ADDR + i);
  79. reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
  80. __raw_writel(reg, WEIM_BASE_ADDR + i);
  81. }
  82. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  83. }
  84. #else
  85. static void setup_iomux_nand(void)
  86. {
  87. }
  88. #endif
  89. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  90. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  91. static void setup_iomux_uart(void)
  92. {
  93. static const iomux_v3_cfg_t uart_pads[] = {
  94. NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
  95. NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
  96. };
  97. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  98. }
  99. #ifdef CONFIG_FSL_ESDHC_IMX
  100. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  101. {MMC_SDHC1_BASE_ADDR},
  102. {MMC_SDHC2_BASE_ADDR},
  103. };
  104. int board_mmc_getcd(struct mmc *mmc)
  105. {
  106. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  107. int ret;
  108. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
  109. gpio_direction_input(IMX_GPIO_NR(1, 1));
  110. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
  111. gpio_direction_input(IMX_GPIO_NR(1, 4));
  112. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  113. ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
  114. else
  115. ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  116. return ret;
  117. }
  118. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  119. PAD_CTL_PUS_100K_UP)
  120. #define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
  121. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  122. PAD_CTL_DSE_HIGH)
  123. int board_mmc_init(bd_t *bis)
  124. {
  125. static const iomux_v3_cfg_t sd1_pads[] = {
  126. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  127. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
  128. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  129. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  130. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  131. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  132. };
  133. static const iomux_v3_cfg_t sd2_pads[] = {
  134. NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
  135. NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
  136. NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
  137. NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
  138. NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
  139. NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
  140. NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
  141. NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
  142. NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
  143. NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
  144. };
  145. u32 index;
  146. int ret;
  147. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  148. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  149. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  150. switch (index) {
  151. case 0:
  152. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  153. ARRAY_SIZE(sd1_pads));
  154. break;
  155. case 1:
  156. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  157. ARRAY_SIZE(sd2_pads));
  158. break;
  159. default:
  160. printf("Warning: you configured more ESDHC controller"
  161. "(%d) as supported by the board(2)\n",
  162. CONFIG_SYS_FSL_ESDHC_NUM);
  163. return -EINVAL;
  164. }
  165. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  166. if (ret)
  167. return ret;
  168. }
  169. return 0;
  170. }
  171. #endif
  172. static void weim_smc911x_iomux(void)
  173. {
  174. static const iomux_v3_cfg_t weim_smc911x_pads[] = {
  175. /* Data bus */
  176. NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
  177. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  178. NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
  179. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  180. NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
  181. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  182. NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
  183. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  184. NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
  185. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  186. NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
  187. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  188. NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
  189. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  190. NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
  191. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  192. NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
  193. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  194. NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
  195. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  196. NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
  197. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  198. NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
  199. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  200. NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
  201. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  202. NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
  203. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  204. NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
  205. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  206. NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
  207. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  208. /* Address lines */
  209. NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  210. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  211. NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  212. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  213. NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  214. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  215. NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  216. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  217. NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  218. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  219. NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  220. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  221. NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  222. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  223. /* other EIM signals for ethernet */
  224. MX53_PAD_EIM_OE__EMI_WEIM_OE,
  225. MX53_PAD_EIM_RW__EMI_WEIM_RW,
  226. MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
  227. };
  228. /* ETHERNET_INT as GPIO2_31 */
  229. imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
  230. gpio_direction_input(ETHERNET_INT);
  231. /* WEIM bus */
  232. imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
  233. ARRAY_SIZE(weim_smc911x_pads));
  234. }
  235. static void weim_cs1_settings(void)
  236. {
  237. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  238. writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
  239. writel(0x0, &weim_regs->cs1gcr2);
  240. writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
  241. writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
  242. writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
  243. writel(0x0, &weim_regs->cs1wcr2);
  244. writel(0x0, &weim_regs->wcr);
  245. set_chipselect_size(CS0_64M_CS1_64M);
  246. }
  247. int board_early_init_f(void)
  248. {
  249. setup_iomux_nand();
  250. setup_iomux_uart();
  251. return 0;
  252. }
  253. int board_init(void)
  254. {
  255. /* address of boot parameters */
  256. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  257. return 0;
  258. }
  259. int board_eth_init(bd_t *bis)
  260. {
  261. int rc = -ENODEV;
  262. weim_smc911x_iomux();
  263. weim_cs1_settings();
  264. #ifdef CONFIG_SMC911X
  265. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  266. #endif
  267. return rc;
  268. }
  269. int checkboard(void)
  270. {
  271. puts("Board: MX53ARD\n");
  272. return 0;
  273. }