meesc.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2009-2015
  8. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  9. * esd electronic system design gmbh <www.esd.eu>
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <init.h>
  14. #include <serial.h>
  15. #include <vsprintf.h>
  16. #include <asm/io.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/setup.h>
  20. #include <asm/arch/at91sam9_smc.h>
  21. #include <asm/arch/at91_common.h>
  22. #include <asm/arch/at91_pmc.h>
  23. #include <asm/arch/at91_rstc.h>
  24. #include <asm/arch/at91_matrix.h>
  25. #include <asm/arch/at91_pio.h>
  26. #include <asm/arch/clk.h>
  27. #include <netdev.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. /*
  30. * Miscelaneous platform dependent initialisations
  31. */
  32. #ifdef CONFIG_REVISION_TAG
  33. static int hw_rev = -1; /* hardware revision */
  34. int get_hw_rev(void)
  35. {
  36. if (hw_rev >= 0)
  37. return hw_rev;
  38. hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  39. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  40. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  41. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  42. if (hw_rev == 15)
  43. hw_rev = 0;
  44. return hw_rev;
  45. }
  46. #endif /* CONFIG_REVISION_TAG */
  47. #ifdef CONFIG_CMD_NAND
  48. static void meesc_nand_hw_init(void)
  49. {
  50. unsigned long csa;
  51. at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
  52. at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  53. /* Enable CS3 */
  54. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  55. writel(csa, &matrix->csa[0]);
  56. /* Configure SMC CS3 for NAND/SmartMedia */
  57. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  58. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  59. &smc->cs[3].setup);
  60. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  61. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  62. &smc->cs[3].pulse);
  63. writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  64. &smc->cs[3].cycle);
  65. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  66. AT91_SMC_MODE_EXNW_DISABLE |
  67. AT91_SMC_MODE_DBW_8 |
  68. AT91_SMC_MODE_TDF_CYCLE(12),
  69. &smc->cs[3].mode);
  70. /* Configure RDY/BSY */
  71. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  72. /* Enable NandFlash */
  73. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  74. }
  75. #endif /* CONFIG_CMD_NAND */
  76. #ifdef CONFIG_MACB
  77. static void meesc_macb_hw_init(void)
  78. {
  79. at91_periph_clk_enable(ATMEL_ID_EMAC);
  80. at91_macb_hw_init();
  81. }
  82. #endif
  83. /*
  84. * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  85. * controller debugging
  86. * The ET1100 is located at physical address 0x70000000
  87. * Its process memory is located at physical address 0x70001000
  88. */
  89. static void meesc_ethercat_hw_init(void)
  90. {
  91. at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
  92. /* Configure SMC EBI1_CS0 for EtherCAT */
  93. writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
  94. AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
  95. &smc1->cs[0].setup);
  96. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
  97. AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
  98. &smc1->cs[0].pulse);
  99. writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
  100. &smc1->cs[0].cycle);
  101. /*
  102. * Configure behavior at external wait signal, byte-select mode, 16 bit
  103. * data bus width, none data float wait states and TDF optimization
  104. */
  105. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
  106. AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
  107. AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
  108. /* Configure RDY/BSY */
  109. at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
  110. }
  111. int dram_init(void)
  112. {
  113. /* dram_init must store complete ramsize in gd->ram_size */
  114. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  115. PHYS_SDRAM_SIZE);
  116. return 0;
  117. }
  118. int dram_init_banksize(void)
  119. {
  120. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  121. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  122. return 0;
  123. }
  124. int board_eth_init(bd_t *bis)
  125. {
  126. int rc = 0;
  127. #ifdef CONFIG_MACB
  128. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  129. #endif
  130. return rc;
  131. }
  132. #ifdef CONFIG_DISPLAY_BOARDINFO
  133. int checkboard(void)
  134. {
  135. char str[32];
  136. u_char hw_type; /* hardware type */
  137. /* read the "Type" register of the ET1100 controller */
  138. hw_type = readb(CONFIG_ET1100_BASE);
  139. switch (hw_type) {
  140. case 0x11:
  141. case 0x3F:
  142. /* ET1100 present, arch number of MEESC-Board */
  143. gd->bd->bi_arch_number = MACH_TYPE_MEESC;
  144. puts("Board: CAN-EtherCAT Gateway");
  145. break;
  146. case 0xFF:
  147. /* no ET1100 present, arch number of EtherCAN/2-Board */
  148. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  149. puts("Board: EtherCAN/2 Gateway");
  150. /* switch on LED1D */
  151. at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
  152. break;
  153. default:
  154. /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
  155. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  156. printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
  157. puts("Board: EtherCAN/2 Gateway");
  158. break;
  159. }
  160. if (env_get_f("serial#", str, sizeof(str)) > 0) {
  161. puts(", serial# ");
  162. puts(str);
  163. }
  164. #ifdef CONFIG_REVISION_TAG
  165. printf("\nHardware-revision: 1.%d\n", get_hw_rev());
  166. #endif
  167. printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
  168. return 0;
  169. }
  170. #endif /* CONFIG_DISPLAY_BOARDINFO */
  171. #ifdef CONFIG_SERIAL_TAG
  172. void get_board_serial(struct tag_serialnr *serialnr)
  173. {
  174. char *str;
  175. char *serial = env_get("serial#");
  176. if (serial) {
  177. str = strchr(serial, '_');
  178. if (str && (strlen(str) >= 4)) {
  179. serialnr->high = (*(str + 1) << 8) | *(str + 2);
  180. serialnr->low = simple_strtoul(str + 3, NULL, 16);
  181. }
  182. } else {
  183. serialnr->high = 0;
  184. serialnr->low = 0;
  185. }
  186. }
  187. #endif
  188. #ifdef CONFIG_REVISION_TAG
  189. u32 get_board_rev(void)
  190. {
  191. return hw_rev | 0x100;
  192. }
  193. #endif
  194. #ifdef CONFIG_MISC_INIT_R
  195. int misc_init_r(void)
  196. {
  197. char *str;
  198. char buf[32];
  199. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  200. /*
  201. * Normally the processor clock has a divisor of 2.
  202. * In some cases this this needs to be set to 4.
  203. * Check the user has set environment mdiv to 4 to change the divisor.
  204. */
  205. str = env_get("mdiv");
  206. if (str && (strcmp(str, "4") == 0)) {
  207. writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
  208. AT91SAM9_PMC_MDIV_4, &pmc->mckr);
  209. at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
  210. serial_setbrg();
  211. /* Notify the user that the clock is not default */
  212. printf("Setting master clock to %s MHz\n",
  213. strmhz(buf, get_mck_clk_rate()));
  214. }
  215. return 0;
  216. }
  217. #endif /* CONFIG_MISC_INIT_R */
  218. int board_early_init_f(void)
  219. {
  220. at91_periph_clk_enable(ATMEL_ID_UHP);
  221. return 0;
  222. }
  223. int board_init(void)
  224. {
  225. /* initialize ET1100 Controller */
  226. meesc_ethercat_hw_init();
  227. /* adress of boot parameters */
  228. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  229. #ifdef CONFIG_CMD_NAND
  230. meesc_nand_hw_init();
  231. #endif
  232. #ifdef CONFIG_MACB
  233. meesc_macb_hw_init();
  234. #endif
  235. #ifdef CONFIG_AT91_CAN
  236. at91_can_hw_init();
  237. #endif
  238. #ifdef CONFIG_USB_OHCI_NEW
  239. at91_uhp_hw_init();
  240. #endif
  241. return 0;
  242. }