titanium.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/mxc_i2c.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <micrel.h>
  21. #include <miiphy.h>
  22. #include <netdev.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  25. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  26. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  27. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  28. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  30. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  31. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  32. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  33. int dram_init(void)
  34. {
  35. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  36. return 0;
  37. }
  38. iomux_v3_cfg_t const uart1_pads[] = {
  39. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  40. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  41. };
  42. iomux_v3_cfg_t const uart2_pads[] = {
  43. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  44. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  45. };
  46. iomux_v3_cfg_t const uart4_pads[] = {
  47. MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48. MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49. };
  50. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  51. struct i2c_pads_info i2c_pad_info0 = {
  52. .scl = {
  53. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  54. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  55. .gp = IMX_GPIO_NR(5, 27)
  56. },
  57. .sda = {
  58. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  59. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  60. .gp = IMX_GPIO_NR(5, 26)
  61. }
  62. };
  63. struct i2c_pads_info i2c_pad_info2 = {
  64. .scl = {
  65. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  66. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  67. .gp = IMX_GPIO_NR(1, 3)
  68. },
  69. .sda = {
  70. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  71. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  72. .gp = IMX_GPIO_NR(7, 11)
  73. }
  74. };
  75. iomux_v3_cfg_t const usdhc3_pads[] = {
  76. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  83. };
  84. iomux_v3_cfg_t const enet_pads1[] = {
  85. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94. /* pin 35 - 1 (PHY_AD2) on reset */
  95. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  96. /* pin 32 - 1 - (MODE0) all */
  97. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98. /* pin 31 - 1 - (MODE1) all */
  99. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  100. /* pin 28 - 1 - (MODE2) all */
  101. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* pin 27 - 1 - (MODE3) all */
  103. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  105. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. /* pin 42 PHY nRST */
  107. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  108. };
  109. iomux_v3_cfg_t const enet_pads2[] = {
  110. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  111. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  112. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  113. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  114. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  115. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  116. };
  117. iomux_v3_cfg_t nfc_pads[] = {
  118. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  119. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  120. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  121. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  122. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  123. MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  124. MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  125. MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  126. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  130. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  132. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  133. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  134. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  135. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  136. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  137. };
  138. static void setup_gpmi_nand(void)
  139. {
  140. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  141. /* config gpmi nand iomux */
  142. imx_iomux_v3_setup_multiple_pads(nfc_pads,
  143. ARRAY_SIZE(nfc_pads));
  144. /* config gpmi and bch clock to 100 MHz */
  145. clrsetbits_le32(&mxc_ccm->cs2cdr,
  146. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  147. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  148. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  149. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  150. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  151. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  152. /* enable gpmi and bch clock gating */
  153. setbits_le32(&mxc_ccm->CCGR4,
  154. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  155. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  156. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  157. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  158. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  159. /* enable apbh clock gating */
  160. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  161. }
  162. static void setup_iomux_enet(void)
  163. {
  164. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  165. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  166. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  167. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  168. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  169. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  170. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  171. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  172. /* Need delay 10ms according to KSZ9021 spec */
  173. udelay(1000 * 10);
  174. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  175. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  176. }
  177. static void setup_iomux_uart(void)
  178. {
  179. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  180. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  181. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  182. }
  183. #ifdef CONFIG_USB_EHCI_MX6
  184. int board_ehci_hcd_init(int port)
  185. {
  186. return 0;
  187. }
  188. #endif
  189. #ifdef CONFIG_FSL_ESDHC_IMX
  190. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  191. { USDHC3_BASE_ADDR },
  192. };
  193. int board_mmc_getcd(struct mmc *mmc)
  194. {
  195. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  196. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  197. gpio_direction_input(IMX_GPIO_NR(7, 0));
  198. return !gpio_get_value(IMX_GPIO_NR(7, 0));
  199. }
  200. return 0;
  201. }
  202. int board_mmc_init(bd_t *bis)
  203. {
  204. /*
  205. * Only one USDHC controller on titianium
  206. */
  207. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  208. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  209. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  210. }
  211. #endif
  212. int board_phy_config(struct phy_device *phydev)
  213. {
  214. /* min rx data delay */
  215. ksz9021_phy_extended_write(phydev,
  216. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  217. /* min tx data delay */
  218. ksz9021_phy_extended_write(phydev,
  219. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  220. /* max rx/tx clock delay, min rx/tx control */
  221. ksz9021_phy_extended_write(phydev,
  222. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  223. if (phydev->drv->config)
  224. phydev->drv->config(phydev);
  225. return 0;
  226. }
  227. int board_eth_init(bd_t *bis)
  228. {
  229. setup_iomux_enet();
  230. return cpu_eth_init(bis);
  231. }
  232. int board_early_init_f(void)
  233. {
  234. setup_iomux_uart();
  235. return 0;
  236. }
  237. int board_init(void)
  238. {
  239. /* address of boot parameters */
  240. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  241. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  242. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  243. setup_gpmi_nand();
  244. return 0;
  245. }
  246. int checkboard(void)
  247. {
  248. puts("Board: Titanium\n");
  249. return 0;
  250. }
  251. #ifdef CONFIG_CMD_BMODE
  252. static const struct boot_mode board_boot_modes[] = {
  253. /* NAND */
  254. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  255. /* 4 bit bus width */
  256. { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
  257. { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
  258. { NULL, 0 },
  259. };
  260. #endif
  261. int misc_init_r(void)
  262. {
  263. #ifdef CONFIG_CMD_BMODE
  264. add_board_boot_modes(board_boot_modes);
  265. #endif
  266. return 0;
  267. }