at91sam9m10g45ek.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <vsprintf.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/at91sam9g45_matrix.h>
  15. #include <asm/arch/at91sam9_smc.h>
  16. #include <asm/arch/at91_common.h>
  17. #include <asm/arch/gpio.h>
  18. #include <asm/arch/clk.h>
  19. #include <lcd.h>
  20. #include <linux/mtd/rawnand.h>
  21. #include <atmel_lcdc.h>
  22. #include <asm/mach-types.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* ------------------------------------------------------------------------- */
  25. /*
  26. * Miscelaneous platform dependent initialisations
  27. */
  28. #ifdef CONFIG_CMD_NAND
  29. void at91sam9m10g45ek_nand_hw_init(void)
  30. {
  31. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  32. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  33. unsigned long csa;
  34. /* Enable CS3 */
  35. csa = readl(&matrix->ebicsa);
  36. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  37. writel(csa, &matrix->ebicsa);
  38. /* Configure SMC CS3 for NAND/SmartMedia */
  39. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  40. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  41. &smc->cs[3].setup);
  42. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  43. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  44. &smc->cs[3].pulse);
  45. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  46. &smc->cs[3].cycle);
  47. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  48. AT91_SMC_MODE_EXNW_DISABLE |
  49. #ifdef CONFIG_SYS_NAND_DBW_16
  50. AT91_SMC_MODE_DBW_16 |
  51. #else /* CONFIG_SYS_NAND_DBW_8 */
  52. AT91_SMC_MODE_DBW_8 |
  53. #endif
  54. AT91_SMC_MODE_TDF_CYCLE(3),
  55. &smc->cs[3].mode);
  56. at91_periph_clk_enable(ATMEL_ID_PIOC);
  57. /* Configure RDY/BSY */
  58. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  59. /* Enable NandFlash */
  60. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  61. }
  62. #endif
  63. #if defined(CONFIG_SPL_BUILD)
  64. #include <spl.h>
  65. #include <nand.h>
  66. void at91_spl_board_init(void)
  67. {
  68. /*
  69. * On the at91sam9m10g45ek board, the chip wm9711 stays in the
  70. * test mode, so it needs do some action to exit test mode.
  71. */
  72. at91_periph_clk_enable(ATMEL_ID_PIODE);
  73. at91_set_gpio_output(AT91_PIN_PD7, 0);
  74. at91_set_gpio_output(AT91_PIN_PD8, 0);
  75. at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
  76. at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
  77. #ifdef CONFIG_SD_BOOT
  78. at91_mci_hw_init();
  79. #elif CONFIG_NAND_BOOT
  80. at91sam9m10g45ek_nand_hw_init();
  81. #endif
  82. }
  83. #include <asm/arch/atmel_mpddrc.h>
  84. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  85. {
  86. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  87. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  88. ATMEL_MPDDRC_CR_NR_ROW_14 |
  89. ATMEL_MPDDRC_CR_DQMS_SHARED |
  90. ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  91. ddr2->rtr = 0x24b;
  92. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  93. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  94. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  95. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  96. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  97. 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  98. 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  99. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  100. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  101. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  102. 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  103. 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  104. ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  105. 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  106. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  107. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  108. }
  109. void mem_init(void)
  110. {
  111. struct atmel_mpddrc_config ddr2;
  112. ddr2_conf(&ddr2);
  113. at91_system_clk_enable(AT91_PMC_DDR);
  114. /* DDRAM2 Controller initialize */
  115. ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
  116. }
  117. #endif
  118. #ifdef CONFIG_CMD_USB
  119. static void at91sam9m10g45ek_usb_hw_init(void)
  120. {
  121. at91_periph_clk_enable(ATMEL_ID_PIODE);
  122. at91_set_gpio_output(AT91_PIN_PD1, 0);
  123. at91_set_gpio_output(AT91_PIN_PD3, 0);
  124. }
  125. #endif
  126. #ifdef CONFIG_LCD
  127. vidinfo_t panel_info = {
  128. .vl_col = 480,
  129. .vl_row = 272,
  130. .vl_clk = 9000000,
  131. .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
  132. ATMEL_LCDC_INVFRAME_NORMAL,
  133. .vl_bpix = 3,
  134. .vl_tft = 1,
  135. .vl_hsync_len = 45,
  136. .vl_left_margin = 1,
  137. .vl_right_margin = 1,
  138. .vl_vsync_len = 1,
  139. .vl_upper_margin = 40,
  140. .vl_lower_margin = 1,
  141. .mmio = ATMEL_BASE_LCDC,
  142. };
  143. void lcd_enable(void)
  144. {
  145. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  146. }
  147. void lcd_disable(void)
  148. {
  149. at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
  150. }
  151. static void at91sam9m10g45ek_lcd_hw_init(void)
  152. {
  153. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  154. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  155. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  156. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  157. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  158. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  159. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  160. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  161. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  162. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  163. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  164. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  165. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  166. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  167. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  168. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  169. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  170. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  171. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  172. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  173. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  174. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  175. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  176. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  177. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  178. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  179. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  180. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  181. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  182. at91_periph_clk_enable(ATMEL_ID_LCDC);
  183. gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
  184. }
  185. #ifdef CONFIG_LCD_INFO
  186. #include <nand.h>
  187. #include <version.h>
  188. void lcd_show_board_info(void)
  189. {
  190. ulong dram_size, nand_size;
  191. int i;
  192. char temp[32];
  193. lcd_printf ("%s\n", U_BOOT_VERSION);
  194. lcd_printf ("(C) 2008 ATMEL Corp\n");
  195. lcd_printf ("at91support@atmel.com\n");
  196. lcd_printf ("%s CPU at %s MHz\n",
  197. ATMEL_CPU_NAME,
  198. strmhz(temp, get_cpu_clk_rate()));
  199. dram_size = 0;
  200. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  201. dram_size += gd->bd->bi_dram[i].size;
  202. nand_size = 0;
  203. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  204. nand_size += get_nand_dev_by_index(i)->size;
  205. lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
  206. dram_size >> 20,
  207. nand_size >> 20 );
  208. }
  209. #endif /* CONFIG_LCD_INFO */
  210. #endif
  211. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  212. void board_debug_uart_init(void)
  213. {
  214. at91_seriald_hw_init();
  215. }
  216. #endif
  217. #ifdef CONFIG_BOARD_EARLY_INIT_F
  218. int board_early_init_f(void)
  219. {
  220. #ifdef CONFIG_DEBUG_UART
  221. debug_uart_init();
  222. #endif
  223. return 0;
  224. }
  225. #endif
  226. int board_init(void)
  227. {
  228. /* arch number of AT91SAM9M10G45EK-Board */
  229. #ifdef CONFIG_AT91SAM9M10G45EK
  230. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
  231. #elif defined CONFIG_AT91SAM9G45EKES
  232. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
  233. #endif
  234. /* adress of boot parameters */
  235. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  236. #ifdef CONFIG_CMD_NAND
  237. at91sam9m10g45ek_nand_hw_init();
  238. #endif
  239. #ifdef CONFIG_CMD_USB
  240. at91sam9m10g45ek_usb_hw_init();
  241. #endif
  242. #ifdef CONFIG_LCD
  243. at91sam9m10g45ek_lcd_hw_init();
  244. #endif
  245. return 0;
  246. }
  247. int dram_init(void)
  248. {
  249. gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
  250. CONFIG_SYS_SDRAM_SIZE);
  251. return 0;
  252. }
  253. #ifdef CONFIG_RESET_PHY_R
  254. void reset_phy(void)
  255. {
  256. }
  257. #endif