vexpress_common.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. */
  18. #include <common.h>
  19. #include <cpu_func.h>
  20. #include <init.h>
  21. #include <malloc.h>
  22. #include <errno.h>
  23. #include <netdev.h>
  24. #include <asm/io.h>
  25. #include <asm/mach-types.h>
  26. #include <asm/arch/systimer.h>
  27. #include <asm/arch/sysctrl.h>
  28. #include <asm/arch/wdt.h>
  29. #include "../drivers/mmc/arm_pl180_mmci.h"
  30. static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
  31. static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
  32. static void flash__init(void);
  33. static void vexpress_timer_init(void);
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  36. void show_boot_progress(int progress)
  37. {
  38. printf("Boot reached stage %d\n", progress);
  39. }
  40. #endif
  41. static inline void delay(ulong loops)
  42. {
  43. __asm__ volatile ("1:\n"
  44. "subs %0, %1, #1\n"
  45. "bne 1b" : "=r" (loops) : "0" (loops));
  46. }
  47. int board_init(void)
  48. {
  49. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  50. gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
  51. gd->flags = 0;
  52. icache_enable();
  53. flash__init();
  54. vexpress_timer_init();
  55. return 0;
  56. }
  57. int board_eth_init(bd_t *bis)
  58. {
  59. int rc = 0;
  60. #ifdef CONFIG_SMC911X
  61. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  62. #endif
  63. return rc;
  64. }
  65. int cpu_mmc_init(bd_t *bis)
  66. {
  67. int rc = 0;
  68. (void) bis;
  69. #ifdef CONFIG_ARM_PL180_MMCI
  70. struct pl180_mmc_host *host;
  71. struct mmc *mmc;
  72. host = malloc(sizeof(struct pl180_mmc_host));
  73. if (!host)
  74. return -ENOMEM;
  75. memset(host, 0, sizeof(*host));
  76. strcpy(host->name, "MMC");
  77. host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
  78. host->pwr_init = INIT_PWR;
  79. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
  80. host->voltages = VOLTAGE_WINDOW_MMC;
  81. host->caps = 0;
  82. host->clock_in = ARM_MCLK;
  83. host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  84. host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
  85. rc = arm_pl180_mmci_init(host, &mmc);
  86. #endif
  87. return rc;
  88. }
  89. static void flash__init(void)
  90. {
  91. /* Setup the sytem control register to allow writing to flash */
  92. writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
  93. &sysctrl_base->scflashctrl);
  94. }
  95. int dram_init(void)
  96. {
  97. gd->ram_size =
  98. get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
  99. return 0;
  100. }
  101. int dram_init_banksize(void)
  102. {
  103. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  104. gd->bd->bi_dram[0].size =
  105. get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  106. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  107. gd->bd->bi_dram[1].size =
  108. get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  109. return 0;
  110. }
  111. /*
  112. * Start timer:
  113. * Setup a 32 bit timer, running at 1KHz
  114. * Versatile Express Motherboard provides 1 MHz timer
  115. */
  116. static void vexpress_timer_init(void)
  117. {
  118. /*
  119. * Set clock frequency in system controller:
  120. * VEXPRESS_REFCLK is 32KHz
  121. * VEXPRESS_TIMCLK is 1MHz
  122. */
  123. writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
  124. SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
  125. readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
  126. /*
  127. * Set Timer0 to be:
  128. * Enabled, free running, no interrupt, 32-bit, wrapping
  129. */
  130. writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
  131. writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
  132. writel(SYSTIMER_EN | SYSTIMER_32BIT |
  133. readl(&systimer_base->timer0control),
  134. &systimer_base->timer0control);
  135. }
  136. int v2m_cfg_write(u32 devfn, u32 data)
  137. {
  138. /* Configuration interface broken? */
  139. u32 val;
  140. devfn |= SYS_CFG_START | SYS_CFG_WRITE;
  141. val = readl(V2M_SYS_CFGSTAT);
  142. writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
  143. writel(data, V2M_SYS_CFGDATA);
  144. writel(devfn, V2M_SYS_CFGCTRL);
  145. do {
  146. val = readl(V2M_SYS_CFGSTAT);
  147. } while (val == 0);
  148. return !!(val & SYS_CFG_ERR);
  149. }
  150. /* Use the ARM Watchdog System to cause reset */
  151. void reset_cpu(ulong addr)
  152. {
  153. if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
  154. printf("Unable to reboot\n");
  155. }
  156. void lowlevel_init(void)
  157. {
  158. }
  159. ulong get_board_rev(void){
  160. return readl((u32 *)SYS_ID);
  161. }
  162. #ifdef CONFIG_ARMV7_NONSEC
  163. /* Setting the address at which secondary cores start from.
  164. * Versatile Express uses one address for all cores, so ignore corenr
  165. */
  166. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  167. {
  168. /* The SYSFLAGS register on VExpress needs to be cleared first
  169. * by writing to the next address, since any writes to the address
  170. * at offset 0 will only be ORed in
  171. */
  172. writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
  173. writel(addr, CONFIG_SYSFLAGS_ADDR);
  174. }
  175. #endif