board.c 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <ns16550.h>
  11. #include <spl.h>
  12. #include <asm/io.h>
  13. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  14. #include <asm/arch/clock.h>
  15. #endif
  16. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  17. #include <asm/arch/funcmux.h>
  18. #endif
  19. #if IS_ENABLED(CONFIG_TEGRA_MC)
  20. #include <asm/arch/mc.h>
  21. #endif
  22. #include <asm/arch/tegra.h>
  23. #include <asm/arch-tegra/ap.h>
  24. #include <asm/arch-tegra/board.h>
  25. #include <asm/arch-tegra/cboot.h>
  26. #include <asm/arch-tegra/pmc.h>
  27. #include <asm/arch-tegra/sys_proto.h>
  28. #include <asm/arch-tegra/warmboot.h>
  29. void save_boot_params_ret(void);
  30. DECLARE_GLOBAL_DATA_PTR;
  31. enum {
  32. /* UARTs which we can enable */
  33. UARTA = 1 << 0,
  34. UARTB = 1 << 1,
  35. UARTC = 1 << 2,
  36. UARTD = 1 << 3,
  37. UARTE = 1 << 4,
  38. UART_COUNT = 5,
  39. };
  40. static bool from_spl __attribute__ ((section(".data")));
  41. #ifndef CONFIG_SPL_BUILD
  42. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  43. unsigned long r3)
  44. {
  45. from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  46. /*
  47. * The logic for this is somewhat indirect. The purpose of the marker
  48. * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
  49. * was loaded from a read-only instance of itself, which is something
  50. * that can happen in secure boot setups. So basically the presence
  51. * of the marker is an indication that U-Boot was loaded by one such
  52. * special variant of U-Boot. Conversely, the absence of the marker
  53. * indicates that this instance of U-Boot was loaded by something
  54. * other than a special U-Boot. This could be SPL, but it could just
  55. * as well be one of any number of other first stage bootloaders.
  56. */
  57. if (from_spl)
  58. cboot_save_boot_params(r0, r1, r2, r3);
  59. save_boot_params_ret();
  60. }
  61. #endif
  62. bool spl_was_boot_source(void)
  63. {
  64. return from_spl;
  65. }
  66. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  67. #if !defined(CONFIG_TEGRA124)
  68. #error tegra_cpu_is_non_secure has only been validated on Tegra124
  69. #endif
  70. bool tegra_cpu_is_non_secure(void)
  71. {
  72. /*
  73. * This register reads 0xffffffff in non-secure mode. This register
  74. * only implements bits 31:20, so the lower bits will always read 0 in
  75. * secure mode. Thus, the lower bits are an indicator for secure vs.
  76. * non-secure mode.
  77. */
  78. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  79. uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  80. return (mc_s_cfg0 & 1) == 1;
  81. }
  82. #endif
  83. #if IS_ENABLED(CONFIG_TEGRA_MC)
  84. /* Read the RAM size directly from the memory controller */
  85. static phys_size_t query_sdram_size(void)
  86. {
  87. struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  88. u32 emem_cfg;
  89. phys_size_t size_bytes;
  90. emem_cfg = readl(&mc->mc_emem_cfg);
  91. #if defined(CONFIG_TEGRA20)
  92. debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  93. size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  94. #else
  95. debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  96. #ifndef CONFIG_PHYS_64BIT
  97. /*
  98. * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  99. * and will wrap. Clip the reported size to the maximum that a 32-bit
  100. * variable can represent (rounded to a page).
  101. */
  102. if (emem_cfg >= 4096) {
  103. size_bytes = U32_MAX & ~(0x1000 - 1);
  104. } else
  105. #endif
  106. {
  107. /* RAM size EMC is programmed to. */
  108. size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
  109. #ifndef CONFIG_ARM64
  110. /*
  111. * If all RAM fits within 32-bits, it can be accessed without
  112. * LPAE, so go test the RAM size. Otherwise, we can't access
  113. * all the RAM, and get_ram_size() would get confused, so
  114. * avoid using it. There's no reason we should need this
  115. * validation step anyway.
  116. */
  117. if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  118. size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  119. size_bytes);
  120. #endif
  121. }
  122. #endif
  123. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  124. /* External memory limited to 2047 MB due to IROM/HI-VEC */
  125. if (size_bytes == SZ_2G)
  126. size_bytes -= SZ_1M;
  127. #endif
  128. return size_bytes;
  129. }
  130. #endif
  131. int dram_init(void)
  132. {
  133. int err;
  134. /* try to initialize DRAM from cboot DTB first */
  135. err = cboot_dram_init();
  136. if (err == 0)
  137. return 0;
  138. #if IS_ENABLED(CONFIG_TEGRA_MC)
  139. /* We do not initialise DRAM here. We just query the size */
  140. gd->ram_size = query_sdram_size();
  141. #endif
  142. return 0;
  143. }
  144. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  145. static int uart_configs[] = {
  146. #if defined(CONFIG_TEGRA20)
  147. #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  148. FUNCMUX_UART1_UAA_UAB,
  149. #elif defined(CONFIG_TEGRA_UARTA_GPU)
  150. FUNCMUX_UART1_GPU,
  151. #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  152. FUNCMUX_UART1_SDIO1,
  153. #else
  154. FUNCMUX_UART1_IRRX_IRTX,
  155. #endif
  156. FUNCMUX_UART2_UAD,
  157. -1,
  158. FUNCMUX_UART4_GMC,
  159. -1,
  160. #elif defined(CONFIG_TEGRA30)
  161. FUNCMUX_UART1_ULPI, /* UARTA */
  162. -1,
  163. -1,
  164. -1,
  165. -1,
  166. #elif defined(CONFIG_TEGRA114)
  167. -1,
  168. -1,
  169. -1,
  170. FUNCMUX_UART4_GMI, /* UARTD */
  171. -1,
  172. #elif defined(CONFIG_TEGRA124)
  173. FUNCMUX_UART1_KBC, /* UARTA */
  174. -1,
  175. -1,
  176. FUNCMUX_UART4_GPIO, /* UARTD */
  177. -1,
  178. #else /* Tegra210 */
  179. FUNCMUX_UART1_UART1, /* UARTA */
  180. -1,
  181. -1,
  182. FUNCMUX_UART4_UART4, /* UARTD */
  183. -1,
  184. #endif
  185. };
  186. /**
  187. * Set up the specified uarts
  188. *
  189. * @param uarts_ids Mask containing UARTs to init (UARTx)
  190. */
  191. static void setup_uarts(int uart_ids)
  192. {
  193. static enum periph_id id_for_uart[] = {
  194. PERIPH_ID_UART1,
  195. PERIPH_ID_UART2,
  196. PERIPH_ID_UART3,
  197. PERIPH_ID_UART4,
  198. PERIPH_ID_UART5,
  199. };
  200. size_t i;
  201. for (i = 0; i < UART_COUNT; i++) {
  202. if (uart_ids & (1 << i)) {
  203. enum periph_id id = id_for_uart[i];
  204. funcmux_select(id, uart_configs[i]);
  205. clock_ll_start_uart(id);
  206. }
  207. }
  208. }
  209. #endif
  210. void board_init_uart_f(void)
  211. {
  212. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  213. int uart_ids = 0; /* bit mask of which UART ids to enable */
  214. #ifdef CONFIG_TEGRA_ENABLE_UARTA
  215. uart_ids |= UARTA;
  216. #endif
  217. #ifdef CONFIG_TEGRA_ENABLE_UARTB
  218. uart_ids |= UARTB;
  219. #endif
  220. #ifdef CONFIG_TEGRA_ENABLE_UARTC
  221. uart_ids |= UARTC;
  222. #endif
  223. #ifdef CONFIG_TEGRA_ENABLE_UARTD
  224. uart_ids |= UARTD;
  225. #endif
  226. #ifdef CONFIG_TEGRA_ENABLE_UARTE
  227. uart_ids |= UARTE;
  228. #endif
  229. setup_uarts(uart_ids);
  230. #endif
  231. }
  232. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  233. static struct ns16550_platdata ns16550_com1_pdata = {
  234. .base = CONFIG_SYS_NS16550_COM1,
  235. .reg_shift = 2,
  236. .clock = CONFIG_SYS_NS16550_CLK,
  237. .fcr = UART_FCR_DEFVAL,
  238. };
  239. U_BOOT_DEVICE(ns16550_com1) = {
  240. "ns16550_serial", &ns16550_com1_pdata
  241. };
  242. #endif
  243. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  244. void enable_caches(void)
  245. {
  246. /* Enable D-cache. I-cache is already enabled in start.S */
  247. dcache_enable();
  248. }
  249. #endif