dram.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #if defined(CONFIG_ARCH_MVEBU)
  14. /* Use common XOR definitions for A3x and AXP */
  15. #include "../../../drivers/ddr/marvell/axp/xor.h"
  16. #include "../../../drivers/ddr/marvell/axp/xor_regs.h"
  17. #endif
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct sdram_bank {
  20. u32 win_bar;
  21. u32 win_sz;
  22. };
  23. struct sdram_addr_dec {
  24. struct sdram_bank sdram_bank[4];
  25. };
  26. #define REG_CPUCS_WIN_ENABLE (1 << 0)
  27. #define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
  28. #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
  29. #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
  30. #ifndef MVEBU_SDRAM_SIZE_MAX
  31. #define MVEBU_SDRAM_SIZE_MAX 0xc0000000
  32. #endif
  33. #define SCRUB_MAGIC 0xbeefdead
  34. #define SCRB_XOR_UNIT 0
  35. #define SCRB_XOR_CHAN 1
  36. #define SCRB_XOR_WIN 0
  37. #define XEBARX_BASE_OFFS 16
  38. /*
  39. * mvebu_sdram_bar - reads SDRAM Base Address Register
  40. */
  41. u32 mvebu_sdram_bar(enum memory_bank bank)
  42. {
  43. struct sdram_addr_dec *base =
  44. (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
  45. u32 result = 0;
  46. u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
  47. if ((!enable) || (bank > BANK3))
  48. return 0;
  49. result = readl(&base->sdram_bank[bank].win_bar);
  50. return result;
  51. }
  52. /*
  53. * mvebu_sdram_bs_set - writes SDRAM Bank size
  54. */
  55. static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
  56. {
  57. struct sdram_addr_dec *base =
  58. (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
  59. /* Read current register value */
  60. u32 reg = readl(&base->sdram_bank[bank].win_sz);
  61. /* Clear window size */
  62. reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
  63. /* Set new window size */
  64. reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
  65. writel(reg, &base->sdram_bank[bank].win_sz);
  66. }
  67. /*
  68. * mvebu_sdram_bs - reads SDRAM Bank size
  69. */
  70. u32 mvebu_sdram_bs(enum memory_bank bank)
  71. {
  72. struct sdram_addr_dec *base =
  73. (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
  74. u32 result = 0;
  75. u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
  76. if ((!enable) || (bank > BANK3))
  77. return 0;
  78. result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
  79. result += 0x01000000;
  80. return result;
  81. }
  82. void mvebu_sdram_size_adjust(enum memory_bank bank)
  83. {
  84. u32 size;
  85. /* probe currently equipped RAM size */
  86. size = get_ram_size((void *)mvebu_sdram_bar(bank),
  87. mvebu_sdram_bs(bank));
  88. /* adjust SDRAM window size accordingly */
  89. mvebu_sdram_bs_set(bank, size);
  90. }
  91. #if defined(CONFIG_ARCH_MVEBU)
  92. static u32 xor_ctrl_save;
  93. static u32 xor_base_save;
  94. static u32 xor_mask_save;
  95. static void mv_xor_init2(u32 cs)
  96. {
  97. u32 reg, base, size, base2;
  98. u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
  99. xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
  100. SCRB_XOR_CHAN));
  101. xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
  102. SCRB_XOR_WIN));
  103. xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
  104. SCRB_XOR_WIN));
  105. /* Enable Window x for each CS */
  106. reg = 0x1;
  107. reg |= (0x3 << 16);
  108. reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
  109. base = 0;
  110. size = mvebu_sdram_bs(cs) - 1;
  111. if (size) {
  112. base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
  113. bank_attr[cs];
  114. reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
  115. base2);
  116. base += size + 1;
  117. size = (size / (64 << 10)) << 16;
  118. /* Window x - size - 256 MB */
  119. reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
  120. }
  121. mv_xor_hal_init(0);
  122. return;
  123. }
  124. static void mv_xor_finish2(void)
  125. {
  126. reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
  127. xor_ctrl_save);
  128. reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
  129. xor_base_save);
  130. reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
  131. xor_mask_save);
  132. }
  133. static void dram_ecc_scrubbing(void)
  134. {
  135. int cs;
  136. u32 size, temp;
  137. u32 total_mem = 0;
  138. u64 total;
  139. u32 start_addr;
  140. /*
  141. * The DDR training code from the bin_hdr / SPL already
  142. * scrubbed the DDR till 0x1000000. And the main U-Boot
  143. * is loaded to an address < 0x1000000. So we need to
  144. * skip this range to not re-scrub this area again.
  145. */
  146. temp = reg_read(REG_SDRAM_CONFIG_ADDR);
  147. temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
  148. reg_write(REG_SDRAM_CONFIG_ADDR, temp);
  149. for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
  150. size = mvebu_sdram_bs(cs);
  151. if (size == 0)
  152. continue;
  153. total = (u64)size;
  154. total_mem += (u32)(total / (1 << 30));
  155. start_addr = 0;
  156. mv_xor_init2(cs);
  157. /* Skip first 16 MiB */
  158. if (0 == cs) {
  159. start_addr = 0x1000000;
  160. size -= start_addr;
  161. }
  162. mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
  163. SCRUB_MAGIC, SCRUB_MAGIC);
  164. /* Wait for previous transfer completion */
  165. while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
  166. ;
  167. mv_xor_finish2();
  168. }
  169. temp = reg_read(REG_SDRAM_CONFIG_ADDR);
  170. temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
  171. reg_write(REG_SDRAM_CONFIG_ADDR, temp);
  172. }
  173. static int ecc_enabled(void)
  174. {
  175. if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
  176. return 1;
  177. return 0;
  178. }
  179. /* Return the width of the DRAM bus, or 0 for unknown. */
  180. static int bus_width(void)
  181. {
  182. int full_width = 0;
  183. if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
  184. full_width = 1;
  185. switch (mvebu_soc_family()) {
  186. case MVEBU_SOC_AXP:
  187. return full_width ? 64 : 32;
  188. break;
  189. case MVEBU_SOC_A375:
  190. case MVEBU_SOC_A38X:
  191. case MVEBU_SOC_MSYS:
  192. return full_width ? 32 : 16;
  193. default:
  194. return 0;
  195. }
  196. }
  197. static int cycle_mode(void)
  198. {
  199. int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
  200. return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
  201. }
  202. #else
  203. static void dram_ecc_scrubbing(void)
  204. {
  205. }
  206. static int ecc_enabled(void)
  207. {
  208. return 0;
  209. }
  210. #endif
  211. int dram_init(void)
  212. {
  213. u64 size = 0;
  214. int i;
  215. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  216. /*
  217. * It is assumed that all memory banks are consecutive
  218. * and without gaps.
  219. * If the gap is found, ram_size will be reported for
  220. * consecutive memory only
  221. */
  222. if (mvebu_sdram_bar(i) != size)
  223. break;
  224. /*
  225. * Don't report more than 3GiB of SDRAM, otherwise there is no
  226. * address space left for the internal registers etc.
  227. */
  228. size += mvebu_sdram_bs(i);
  229. if (size > MVEBU_SDRAM_SIZE_MAX)
  230. size = MVEBU_SDRAM_SIZE_MAX;
  231. }
  232. if (ecc_enabled())
  233. dram_ecc_scrubbing();
  234. gd->ram_size = size;
  235. return 0;
  236. }
  237. /*
  238. * If this function is not defined here,
  239. * board.c alters dram bank zero configuration defined above.
  240. */
  241. int dram_init_banksize(void)
  242. {
  243. u64 size = 0;
  244. int i;
  245. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  246. gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
  247. gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
  248. /* Clip the banksize to 1GiB if it exceeds the max size */
  249. size += gd->bd->bi_dram[i].size;
  250. if (size > MVEBU_SDRAM_SIZE_MAX)
  251. mvebu_sdram_bs_set(i, 0x40000000);
  252. }
  253. return 0;
  254. }
  255. #if defined(CONFIG_ARCH_MVEBU)
  256. void board_add_ram_info(int use_default)
  257. {
  258. struct sar_freq_modes sar_freq;
  259. int mode;
  260. int width;
  261. get_sar_freq(&sar_freq);
  262. printf(" (%d MHz, ", sar_freq.d_clk);
  263. width = bus_width();
  264. if (width)
  265. printf("%d-bit, ", width);
  266. mode = cycle_mode();
  267. /* Mode 0 = Single cycle
  268. * Mode 1 = Two cycles (2T)
  269. * Mode 2 = Three cycles (3T)
  270. */
  271. if (mode == 1)
  272. printf("2T, ");
  273. if (mode == 2)
  274. printf("3T, ");
  275. if (ecc_enabled())
  276. printf("ECC");
  277. else
  278. printf("ECC not");
  279. printf(" enabled)");
  280. }
  281. #endif