spl_mem_init.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 RAM init
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <linux/compiler.h>
  15. #include "mxs_init.h"
  16. __weak uint32_t mxs_dram_vals[] = {
  17. /*
  18. * i.MX28 DDR2 at 200MHz
  19. */
  20. #if defined(CONFIG_MX28)
  21. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  22. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  23. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  24. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  25. 0x00000000, 0x00000100, 0x00000000, 0x00000000,
  26. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  27. 0x00000000, 0x00000000, 0x00010101, 0x01010101,
  28. 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
  29. 0x00000100, 0x00000100, 0x00000000, 0x00000002,
  30. 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
  31. 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
  32. 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
  33. 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
  34. 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
  35. 0x00000003, 0x00000000, 0x00000000, 0x00000000,
  36. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  37. 0x00000000, 0x00000000, 0x00000612, 0x01000F02,
  38. 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
  39. 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
  40. 0x07000300, 0x07400300, 0x07400300, 0x00000005,
  41. 0x00000000, 0x00000000, 0x01000000, 0x01020408,
  42. 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
  43. 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
  44. 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
  45. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  46. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  47. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  48. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  49. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  50. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  51. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  52. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  53. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  54. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  55. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  56. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  57. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  58. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  59. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  60. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  61. 0x00000000, 0x00000000, 0x00010000, 0x00030404,
  62. 0x00000003, 0x00000000, 0x00000000, 0x00000000,
  63. 0x00000000, 0x00000000, 0x00000000, 0x01010000,
  64. 0x01000000, 0x03030000, 0x00010303, 0x01020202,
  65. 0x00000000, 0x02040303, 0x21002103, 0x00061200,
  66. 0x06120612, 0x04420442, 0x04420442, 0x00040004,
  67. 0x00040004, 0x00000000, 0x00000000, 0x00000000,
  68. 0x00000000, 0xffffffff
  69. /*
  70. * i.MX23 DDR at 133MHz
  71. */
  72. #elif defined(CONFIG_MX23)
  73. 0x01010001, 0x00010100, 0x01000101, 0x00000001,
  74. 0x00000101, 0x00000000, 0x00010000, 0x01000001,
  75. 0x00000000, 0x00000001, 0x07000200, 0x00070202,
  76. 0x02020000, 0x04040a01, 0x00000201, 0x02040000,
  77. 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
  78. 0x02061521, 0x0000000a, 0x00080008, 0x00200020,
  79. 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
  80. 0x00000000, 0x00000020, 0x00000020, 0x00c80000,
  81. 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
  82. 0x00000101, 0x00040001, 0x00000000, 0x00000000,
  83. 0x00010000
  84. #else
  85. #error Unsupported memory initialization
  86. #endif
  87. };
  88. __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
  89. {
  90. debug("SPL: Using default SDRAM parameters\n");
  91. }
  92. #ifdef CONFIG_MX28
  93. static void initialize_dram_values(void)
  94. {
  95. int i;
  96. debug("SPL: Setting mx28 board specific SDRAM parameters\n");
  97. mxs_adjust_memory_params(mxs_dram_vals);
  98. debug("SPL: Applying SDRAM parameters\n");
  99. for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
  100. writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
  101. }
  102. #else
  103. static void initialize_dram_values(void)
  104. {
  105. int i;
  106. debug("SPL: Setting mx23 board specific SDRAM parameters\n");
  107. mxs_adjust_memory_params(mxs_dram_vals);
  108. /*
  109. * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
  110. * per FSL bootlets code.
  111. *
  112. * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
  113. * "reserved".
  114. * HW_DRAM_CTL8 is setup as the last element.
  115. * So skip the initialization of these HW_DRAM_CTL registers.
  116. */
  117. debug("SPL: Applying SDRAM parameters\n");
  118. for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
  119. if (i == 8 || i == 27 || i == 28 || i == 35)
  120. continue;
  121. writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
  122. }
  123. /*
  124. * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
  125. * element to be set
  126. */
  127. writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
  128. }
  129. #endif
  130. static void mxs_mem_init_clock(void)
  131. {
  132. struct mxs_clkctrl_regs *clkctrl_regs =
  133. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  134. #if defined(CONFIG_MX23)
  135. /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
  136. const unsigned char divider = 33;
  137. #elif defined(CONFIG_MX28)
  138. /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
  139. const unsigned char divider = 21;
  140. #endif
  141. debug("SPL: Initialising FRAC0\n");
  142. /* Gate EMI clock */
  143. writeb(CLKCTRL_FRAC_CLKGATE,
  144. &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
  145. /* Set fractional divider for ref_emi */
  146. writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
  147. &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
  148. /* Ungate EMI clock */
  149. writeb(CLKCTRL_FRAC_CLKGATE,
  150. &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
  151. early_delay(11000);
  152. /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
  153. writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
  154. (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
  155. &clkctrl_regs->hw_clkctrl_emi);
  156. /* Unbypass EMI */
  157. writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
  158. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  159. early_delay(10000);
  160. debug("SPL: FRAC0 Initialised\n");
  161. }
  162. static void mxs_mem_setup_cpu_and_hbus(void)
  163. {
  164. struct mxs_clkctrl_regs *clkctrl_regs =
  165. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  166. debug("SPL: Setting CPU and HBUS clock frequencies\n");
  167. /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
  168. * and ungate CPU clock */
  169. writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
  170. (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
  171. /* Set CPU bypass */
  172. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  173. &clkctrl_regs->hw_clkctrl_clkseq_set);
  174. /* HBUS = 151MHz */
  175. writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
  176. writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
  177. &clkctrl_regs->hw_clkctrl_hbus_clr);
  178. early_delay(10000);
  179. /* CPU clock divider = 1 */
  180. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
  181. CLKCTRL_CPU_DIV_CPU_MASK, 1);
  182. /* Disable CPU bypass */
  183. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  184. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  185. early_delay(15000);
  186. }
  187. static void mxs_mem_setup_vdda(void)
  188. {
  189. struct mxs_power_regs *power_regs =
  190. (struct mxs_power_regs *)MXS_POWER_BASE;
  191. debug("SPL: Configuring VDDA\n");
  192. writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
  193. (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
  194. POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
  195. &power_regs->hw_power_vddactrl);
  196. }
  197. uint32_t mxs_mem_get_size(void)
  198. {
  199. uint32_t sz, da;
  200. uint32_t *vt = (uint32_t *)0x20;
  201. /* The following is "subs pc, r14, #4", used as return from DABT. */
  202. const uint32_t data_abort_memdetect_handler = 0xe25ef004;
  203. /* Replace the DABT handler. */
  204. da = vt[4];
  205. vt[4] = data_abort_memdetect_handler;
  206. sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  207. /* Restore the old DABT handler. */
  208. vt[4] = da;
  209. return sz;
  210. }
  211. #ifdef CONFIG_MX23
  212. static void mx23_mem_setup_vddmem(void)
  213. {
  214. struct mxs_power_regs *power_regs =
  215. (struct mxs_power_regs *)MXS_POWER_BASE;
  216. debug("SPL: Setting mx23 VDDMEM\n");
  217. /* We must wait before and after disabling the current limiter! */
  218. early_delay(10000);
  219. clrbits_le32(&power_regs->hw_power_vddmemctrl,
  220. POWER_VDDMEMCTRL_ENABLE_ILIMIT);
  221. early_delay(10000);
  222. }
  223. static void mx23_mem_init(void)
  224. {
  225. debug("SPL: Initialising mx23 SDRAM Controller\n");
  226. /*
  227. * Reset/ungate the EMI block. This is essential, otherwise the system
  228. * suffers from memory instability. This thing is mx23 specific and is
  229. * no longer present on mx28.
  230. */
  231. mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
  232. mx23_mem_setup_vddmem();
  233. /*
  234. * Configure the DRAM registers
  235. */
  236. /* Clear START and SREFRESH bit from DRAM_CTL8 */
  237. clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
  238. initialize_dram_values();
  239. /* Set START bit in DRAM_CTL8 */
  240. setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
  241. clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
  242. /* Wait for EMI_STAT bit DRAM_HALTED */
  243. for (;;) {
  244. if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
  245. break;
  246. early_delay(1000);
  247. }
  248. /* Adjust EMI port priority. */
  249. clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
  250. early_delay(20000);
  251. setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
  252. setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
  253. }
  254. #endif
  255. #ifdef CONFIG_MX28
  256. static void mx28_mem_init(void)
  257. {
  258. struct mxs_pinctrl_regs *pinctrl_regs =
  259. (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
  260. debug("SPL: Initialising mx28 SDRAM Controller\n");
  261. /* Set DDR2 mode */
  262. writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
  263. &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
  264. /*
  265. * Configure the DRAM registers
  266. */
  267. /* Clear START bit from DRAM_CTL16 */
  268. clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
  269. initialize_dram_values();
  270. /* Clear SREFRESH bit from DRAM_CTL17 */
  271. clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
  272. /* Set START bit in DRAM_CTL16 */
  273. setbits_le32(MXS_DRAM_BASE + 0x40, 1);
  274. /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
  275. while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
  276. ;
  277. }
  278. #endif
  279. void mxs_mem_init(void)
  280. {
  281. early_delay(11000);
  282. mxs_mem_init_clock();
  283. mxs_mem_setup_vdda();
  284. #if defined(CONFIG_MX23)
  285. mx23_mem_init();
  286. #elif defined(CONFIG_MX28)
  287. mx28_mem_init();
  288. #endif
  289. early_delay(10000);
  290. mxs_mem_setup_cpu_and_hbus();
  291. }