brcmnand.c 73 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright © 2010-2015 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <common.h>
  15. #include <asm/io.h>
  16. #include <memalign.h>
  17. #include <nand.h>
  18. #include <clk.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/devres.h>
  21. #include <linux/err.h>
  22. #include <linux/ioport.h>
  23. #include <linux/completion.h>
  24. #include <linux/errno.h>
  25. #include <linux/log2.h>
  26. #include <asm/processor.h>
  27. #include <dm.h>
  28. #include "brcmnand.h"
  29. #include "brcmnand_compat.h"
  30. /*
  31. * This flag controls if WP stays on between erase/write commands to mitigate
  32. * flash corruption due to power glitches. Values:
  33. * 0: NAND_WP is not used or not available
  34. * 1: NAND_WP is set by default, cleared for erase/write operations
  35. * 2: NAND_WP is always cleared
  36. */
  37. static int wp_on = 1;
  38. module_param(wp_on, int, 0444);
  39. /***********************************************************************
  40. * Definitions
  41. ***********************************************************************/
  42. #define DRV_NAME "brcmnand"
  43. #define CMD_NULL 0x00
  44. #define CMD_PAGE_READ 0x01
  45. #define CMD_SPARE_AREA_READ 0x02
  46. #define CMD_STATUS_READ 0x03
  47. #define CMD_PROGRAM_PAGE 0x04
  48. #define CMD_PROGRAM_SPARE_AREA 0x05
  49. #define CMD_COPY_BACK 0x06
  50. #define CMD_DEVICE_ID_READ 0x07
  51. #define CMD_BLOCK_ERASE 0x08
  52. #define CMD_FLASH_RESET 0x09
  53. #define CMD_BLOCKS_LOCK 0x0a
  54. #define CMD_BLOCKS_LOCK_DOWN 0x0b
  55. #define CMD_BLOCKS_UNLOCK 0x0c
  56. #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
  57. #define CMD_PARAMETER_READ 0x0e
  58. #define CMD_PARAMETER_CHANGE_COL 0x0f
  59. #define CMD_LOW_LEVEL_OP 0x10
  60. struct brcm_nand_dma_desc {
  61. u32 next_desc;
  62. u32 next_desc_ext;
  63. u32 cmd_irq;
  64. u32 dram_addr;
  65. u32 dram_addr_ext;
  66. u32 tfr_len;
  67. u32 total_len;
  68. u32 flash_addr;
  69. u32 flash_addr_ext;
  70. u32 cs;
  71. u32 pad2[5];
  72. u32 status_valid;
  73. } __packed;
  74. /* Bitfields for brcm_nand_dma_desc::status_valid */
  75. #define FLASH_DMA_ECC_ERROR (1 << 8)
  76. #define FLASH_DMA_CORR_ERROR (1 << 9)
  77. /* 512B flash cache in the NAND controller HW */
  78. #define FC_SHIFT 9U
  79. #define FC_BYTES 512U
  80. #define FC_WORDS (FC_BYTES >> 2)
  81. #define BRCMNAND_MIN_PAGESIZE 512
  82. #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
  83. #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
  84. #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
  85. #define NAND_POLL_STATUS_TIMEOUT_MS 100
  86. /* Controller feature flags */
  87. enum {
  88. BRCMNAND_HAS_1K_SECTORS = BIT(0),
  89. BRCMNAND_HAS_PREFETCH = BIT(1),
  90. BRCMNAND_HAS_CACHE_MODE = BIT(2),
  91. BRCMNAND_HAS_WP = BIT(3),
  92. };
  93. struct brcmnand_controller {
  94. #ifndef __UBOOT__
  95. struct device *dev;
  96. #else
  97. struct udevice *dev;
  98. #endif /* __UBOOT__ */
  99. struct nand_hw_control controller;
  100. void __iomem *nand_base;
  101. void __iomem *nand_fc; /* flash cache */
  102. void __iomem *flash_dma_base;
  103. unsigned int irq;
  104. unsigned int dma_irq;
  105. int nand_version;
  106. int parameter_page_big_endian;
  107. /* Some SoCs provide custom interrupt status register(s) */
  108. struct brcmnand_soc *soc;
  109. /* Some SoCs have a gateable clock for the controller */
  110. struct clk *clk;
  111. int cmd_pending;
  112. bool dma_pending;
  113. struct completion done;
  114. struct completion dma_done;
  115. /* List of NAND hosts (one for each chip-select) */
  116. struct list_head host_list;
  117. struct brcm_nand_dma_desc *dma_desc;
  118. dma_addr_t dma_pa;
  119. /* in-memory cache of the FLASH_CACHE, used only for some commands */
  120. u8 flash_cache[FC_BYTES];
  121. /* Controller revision details */
  122. const u16 *reg_offsets;
  123. unsigned int reg_spacing; /* between CS1, CS2, ... regs */
  124. const u8 *cs_offsets; /* within each chip-select */
  125. const u8 *cs0_offsets; /* within CS0, if different */
  126. unsigned int max_block_size;
  127. const unsigned int *block_sizes;
  128. unsigned int max_page_size;
  129. const unsigned int *page_sizes;
  130. unsigned int max_oob;
  131. u32 features;
  132. /* for low-power standby/resume only */
  133. u32 nand_cs_nand_select;
  134. u32 nand_cs_nand_xor;
  135. u32 corr_stat_threshold;
  136. u32 flash_dma_mode;
  137. };
  138. struct brcmnand_cfg {
  139. u64 device_size;
  140. unsigned int block_size;
  141. unsigned int page_size;
  142. unsigned int spare_area_size;
  143. unsigned int device_width;
  144. unsigned int col_adr_bytes;
  145. unsigned int blk_adr_bytes;
  146. unsigned int ful_adr_bytes;
  147. unsigned int sector_size_1k;
  148. unsigned int ecc_level;
  149. /* use for low-power standby/resume only */
  150. u32 acc_control;
  151. u32 config;
  152. u32 config_ext;
  153. u32 timing_1;
  154. u32 timing_2;
  155. };
  156. struct brcmnand_host {
  157. struct list_head node;
  158. struct nand_chip chip;
  159. #ifndef __UBOOT__
  160. struct platform_device *pdev;
  161. #else
  162. struct udevice *pdev;
  163. #endif /* __UBOOT__ */
  164. int cs;
  165. unsigned int last_cmd;
  166. unsigned int last_byte;
  167. u64 last_addr;
  168. struct brcmnand_cfg hwcfg;
  169. struct brcmnand_controller *ctrl;
  170. };
  171. enum brcmnand_reg {
  172. BRCMNAND_CMD_START = 0,
  173. BRCMNAND_CMD_EXT_ADDRESS,
  174. BRCMNAND_CMD_ADDRESS,
  175. BRCMNAND_INTFC_STATUS,
  176. BRCMNAND_CS_SELECT,
  177. BRCMNAND_CS_XOR,
  178. BRCMNAND_LL_OP,
  179. BRCMNAND_CS0_BASE,
  180. BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
  181. BRCMNAND_CORR_THRESHOLD,
  182. BRCMNAND_CORR_THRESHOLD_EXT,
  183. BRCMNAND_UNCORR_COUNT,
  184. BRCMNAND_CORR_COUNT,
  185. BRCMNAND_CORR_EXT_ADDR,
  186. BRCMNAND_CORR_ADDR,
  187. BRCMNAND_UNCORR_EXT_ADDR,
  188. BRCMNAND_UNCORR_ADDR,
  189. BRCMNAND_SEMAPHORE,
  190. BRCMNAND_ID,
  191. BRCMNAND_ID_EXT,
  192. BRCMNAND_LL_RDATA,
  193. BRCMNAND_OOB_READ_BASE,
  194. BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
  195. BRCMNAND_OOB_WRITE_BASE,
  196. BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
  197. BRCMNAND_FC_BASE,
  198. };
  199. /* BRCMNAND v4.0 */
  200. static const u16 brcmnand_regs_v40[] = {
  201. [BRCMNAND_CMD_START] = 0x04,
  202. [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
  203. [BRCMNAND_CMD_ADDRESS] = 0x0c,
  204. [BRCMNAND_INTFC_STATUS] = 0x6c,
  205. [BRCMNAND_CS_SELECT] = 0x14,
  206. [BRCMNAND_CS_XOR] = 0x18,
  207. [BRCMNAND_LL_OP] = 0x178,
  208. [BRCMNAND_CS0_BASE] = 0x40,
  209. [BRCMNAND_CS1_BASE] = 0xd0,
  210. [BRCMNAND_CORR_THRESHOLD] = 0x84,
  211. [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
  212. [BRCMNAND_UNCORR_COUNT] = 0,
  213. [BRCMNAND_CORR_COUNT] = 0,
  214. [BRCMNAND_CORR_EXT_ADDR] = 0x70,
  215. [BRCMNAND_CORR_ADDR] = 0x74,
  216. [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
  217. [BRCMNAND_UNCORR_ADDR] = 0x7c,
  218. [BRCMNAND_SEMAPHORE] = 0x58,
  219. [BRCMNAND_ID] = 0x60,
  220. [BRCMNAND_ID_EXT] = 0x64,
  221. [BRCMNAND_LL_RDATA] = 0x17c,
  222. [BRCMNAND_OOB_READ_BASE] = 0x20,
  223. [BRCMNAND_OOB_READ_10_BASE] = 0x130,
  224. [BRCMNAND_OOB_WRITE_BASE] = 0x30,
  225. [BRCMNAND_OOB_WRITE_10_BASE] = 0,
  226. [BRCMNAND_FC_BASE] = 0x200,
  227. };
  228. /* BRCMNAND v5.0 */
  229. static const u16 brcmnand_regs_v50[] = {
  230. [BRCMNAND_CMD_START] = 0x04,
  231. [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
  232. [BRCMNAND_CMD_ADDRESS] = 0x0c,
  233. [BRCMNAND_INTFC_STATUS] = 0x6c,
  234. [BRCMNAND_CS_SELECT] = 0x14,
  235. [BRCMNAND_CS_XOR] = 0x18,
  236. [BRCMNAND_LL_OP] = 0x178,
  237. [BRCMNAND_CS0_BASE] = 0x40,
  238. [BRCMNAND_CS1_BASE] = 0xd0,
  239. [BRCMNAND_CORR_THRESHOLD] = 0x84,
  240. [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
  241. [BRCMNAND_UNCORR_COUNT] = 0,
  242. [BRCMNAND_CORR_COUNT] = 0,
  243. [BRCMNAND_CORR_EXT_ADDR] = 0x70,
  244. [BRCMNAND_CORR_ADDR] = 0x74,
  245. [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
  246. [BRCMNAND_UNCORR_ADDR] = 0x7c,
  247. [BRCMNAND_SEMAPHORE] = 0x58,
  248. [BRCMNAND_ID] = 0x60,
  249. [BRCMNAND_ID_EXT] = 0x64,
  250. [BRCMNAND_LL_RDATA] = 0x17c,
  251. [BRCMNAND_OOB_READ_BASE] = 0x20,
  252. [BRCMNAND_OOB_READ_10_BASE] = 0x130,
  253. [BRCMNAND_OOB_WRITE_BASE] = 0x30,
  254. [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
  255. [BRCMNAND_FC_BASE] = 0x200,
  256. };
  257. /* BRCMNAND v6.0 - v7.1 */
  258. static const u16 brcmnand_regs_v60[] = {
  259. [BRCMNAND_CMD_START] = 0x04,
  260. [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
  261. [BRCMNAND_CMD_ADDRESS] = 0x0c,
  262. [BRCMNAND_INTFC_STATUS] = 0x14,
  263. [BRCMNAND_CS_SELECT] = 0x18,
  264. [BRCMNAND_CS_XOR] = 0x1c,
  265. [BRCMNAND_LL_OP] = 0x20,
  266. [BRCMNAND_CS0_BASE] = 0x50,
  267. [BRCMNAND_CS1_BASE] = 0,
  268. [BRCMNAND_CORR_THRESHOLD] = 0xc0,
  269. [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
  270. [BRCMNAND_UNCORR_COUNT] = 0xfc,
  271. [BRCMNAND_CORR_COUNT] = 0x100,
  272. [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
  273. [BRCMNAND_CORR_ADDR] = 0x110,
  274. [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
  275. [BRCMNAND_UNCORR_ADDR] = 0x118,
  276. [BRCMNAND_SEMAPHORE] = 0x150,
  277. [BRCMNAND_ID] = 0x194,
  278. [BRCMNAND_ID_EXT] = 0x198,
  279. [BRCMNAND_LL_RDATA] = 0x19c,
  280. [BRCMNAND_OOB_READ_BASE] = 0x200,
  281. [BRCMNAND_OOB_READ_10_BASE] = 0,
  282. [BRCMNAND_OOB_WRITE_BASE] = 0x280,
  283. [BRCMNAND_OOB_WRITE_10_BASE] = 0,
  284. [BRCMNAND_FC_BASE] = 0x400,
  285. };
  286. /* BRCMNAND v7.1 */
  287. static const u16 brcmnand_regs_v71[] = {
  288. [BRCMNAND_CMD_START] = 0x04,
  289. [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
  290. [BRCMNAND_CMD_ADDRESS] = 0x0c,
  291. [BRCMNAND_INTFC_STATUS] = 0x14,
  292. [BRCMNAND_CS_SELECT] = 0x18,
  293. [BRCMNAND_CS_XOR] = 0x1c,
  294. [BRCMNAND_LL_OP] = 0x20,
  295. [BRCMNAND_CS0_BASE] = 0x50,
  296. [BRCMNAND_CS1_BASE] = 0,
  297. [BRCMNAND_CORR_THRESHOLD] = 0xdc,
  298. [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
  299. [BRCMNAND_UNCORR_COUNT] = 0xfc,
  300. [BRCMNAND_CORR_COUNT] = 0x100,
  301. [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
  302. [BRCMNAND_CORR_ADDR] = 0x110,
  303. [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
  304. [BRCMNAND_UNCORR_ADDR] = 0x118,
  305. [BRCMNAND_SEMAPHORE] = 0x150,
  306. [BRCMNAND_ID] = 0x194,
  307. [BRCMNAND_ID_EXT] = 0x198,
  308. [BRCMNAND_LL_RDATA] = 0x19c,
  309. [BRCMNAND_OOB_READ_BASE] = 0x200,
  310. [BRCMNAND_OOB_READ_10_BASE] = 0,
  311. [BRCMNAND_OOB_WRITE_BASE] = 0x280,
  312. [BRCMNAND_OOB_WRITE_10_BASE] = 0,
  313. [BRCMNAND_FC_BASE] = 0x400,
  314. };
  315. /* BRCMNAND v7.2 */
  316. static const u16 brcmnand_regs_v72[] = {
  317. [BRCMNAND_CMD_START] = 0x04,
  318. [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
  319. [BRCMNAND_CMD_ADDRESS] = 0x0c,
  320. [BRCMNAND_INTFC_STATUS] = 0x14,
  321. [BRCMNAND_CS_SELECT] = 0x18,
  322. [BRCMNAND_CS_XOR] = 0x1c,
  323. [BRCMNAND_LL_OP] = 0x20,
  324. [BRCMNAND_CS0_BASE] = 0x50,
  325. [BRCMNAND_CS1_BASE] = 0,
  326. [BRCMNAND_CORR_THRESHOLD] = 0xdc,
  327. [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
  328. [BRCMNAND_UNCORR_COUNT] = 0xfc,
  329. [BRCMNAND_CORR_COUNT] = 0x100,
  330. [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
  331. [BRCMNAND_CORR_ADDR] = 0x110,
  332. [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
  333. [BRCMNAND_UNCORR_ADDR] = 0x118,
  334. [BRCMNAND_SEMAPHORE] = 0x150,
  335. [BRCMNAND_ID] = 0x194,
  336. [BRCMNAND_ID_EXT] = 0x198,
  337. [BRCMNAND_LL_RDATA] = 0x19c,
  338. [BRCMNAND_OOB_READ_BASE] = 0x200,
  339. [BRCMNAND_OOB_READ_10_BASE] = 0,
  340. [BRCMNAND_OOB_WRITE_BASE] = 0x400,
  341. [BRCMNAND_OOB_WRITE_10_BASE] = 0,
  342. [BRCMNAND_FC_BASE] = 0x600,
  343. };
  344. enum brcmnand_cs_reg {
  345. BRCMNAND_CS_CFG_EXT = 0,
  346. BRCMNAND_CS_CFG,
  347. BRCMNAND_CS_ACC_CONTROL,
  348. BRCMNAND_CS_TIMING1,
  349. BRCMNAND_CS_TIMING2,
  350. };
  351. /* Per chip-select offsets for v7.1 */
  352. static const u8 brcmnand_cs_offsets_v71[] = {
  353. [BRCMNAND_CS_ACC_CONTROL] = 0x00,
  354. [BRCMNAND_CS_CFG_EXT] = 0x04,
  355. [BRCMNAND_CS_CFG] = 0x08,
  356. [BRCMNAND_CS_TIMING1] = 0x0c,
  357. [BRCMNAND_CS_TIMING2] = 0x10,
  358. };
  359. /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
  360. static const u8 brcmnand_cs_offsets[] = {
  361. [BRCMNAND_CS_ACC_CONTROL] = 0x00,
  362. [BRCMNAND_CS_CFG_EXT] = 0x04,
  363. [BRCMNAND_CS_CFG] = 0x04,
  364. [BRCMNAND_CS_TIMING1] = 0x08,
  365. [BRCMNAND_CS_TIMING2] = 0x0c,
  366. };
  367. /* Per chip-select offset for <= v5.0 on CS0 only */
  368. static const u8 brcmnand_cs_offsets_cs0[] = {
  369. [BRCMNAND_CS_ACC_CONTROL] = 0x00,
  370. [BRCMNAND_CS_CFG_EXT] = 0x08,
  371. [BRCMNAND_CS_CFG] = 0x08,
  372. [BRCMNAND_CS_TIMING1] = 0x10,
  373. [BRCMNAND_CS_TIMING2] = 0x14,
  374. };
  375. /*
  376. * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
  377. * one config register, but once the bitfields overflowed, newer controllers
  378. * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
  379. */
  380. enum {
  381. CFG_BLK_ADR_BYTES_SHIFT = 8,
  382. CFG_COL_ADR_BYTES_SHIFT = 12,
  383. CFG_FUL_ADR_BYTES_SHIFT = 16,
  384. CFG_BUS_WIDTH_SHIFT = 23,
  385. CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
  386. CFG_DEVICE_SIZE_SHIFT = 24,
  387. /* Only for pre-v7.1 (with no CFG_EXT register) */
  388. CFG_PAGE_SIZE_SHIFT = 20,
  389. CFG_BLK_SIZE_SHIFT = 28,
  390. /* Only for v7.1+ (with CFG_EXT register) */
  391. CFG_EXT_PAGE_SIZE_SHIFT = 0,
  392. CFG_EXT_BLK_SIZE_SHIFT = 4,
  393. };
  394. /* BRCMNAND_INTFC_STATUS */
  395. enum {
  396. INTFC_FLASH_STATUS = GENMASK(7, 0),
  397. INTFC_ERASED = BIT(27),
  398. INTFC_OOB_VALID = BIT(28),
  399. INTFC_CACHE_VALID = BIT(29),
  400. INTFC_FLASH_READY = BIT(30),
  401. INTFC_CTLR_READY = BIT(31),
  402. };
  403. static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
  404. {
  405. return brcmnand_readl(ctrl->nand_base + offs);
  406. }
  407. static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
  408. u32 val)
  409. {
  410. brcmnand_writel(val, ctrl->nand_base + offs);
  411. }
  412. static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
  413. {
  414. static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
  415. static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
  416. static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
  417. ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
  418. /* Only support v4.0+? */
  419. if (ctrl->nand_version < 0x0400) {
  420. dev_err(ctrl->dev, "version %#x not supported\n",
  421. ctrl->nand_version);
  422. return -ENODEV;
  423. }
  424. /* Register offsets */
  425. if (ctrl->nand_version >= 0x0702)
  426. ctrl->reg_offsets = brcmnand_regs_v72;
  427. else if (ctrl->nand_version >= 0x0701)
  428. ctrl->reg_offsets = brcmnand_regs_v71;
  429. else if (ctrl->nand_version >= 0x0600)
  430. ctrl->reg_offsets = brcmnand_regs_v60;
  431. else if (ctrl->nand_version >= 0x0500)
  432. ctrl->reg_offsets = brcmnand_regs_v50;
  433. else if (ctrl->nand_version >= 0x0400)
  434. ctrl->reg_offsets = brcmnand_regs_v40;
  435. /* Chip-select stride */
  436. if (ctrl->nand_version >= 0x0701)
  437. ctrl->reg_spacing = 0x14;
  438. else
  439. ctrl->reg_spacing = 0x10;
  440. /* Per chip-select registers */
  441. if (ctrl->nand_version >= 0x0701) {
  442. ctrl->cs_offsets = brcmnand_cs_offsets_v71;
  443. } else {
  444. ctrl->cs_offsets = brcmnand_cs_offsets;
  445. /* v5.0 and earlier has a different CS0 offset layout */
  446. if (ctrl->nand_version <= 0x0500)
  447. ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
  448. }
  449. /* Page / block sizes */
  450. if (ctrl->nand_version >= 0x0701) {
  451. /* >= v7.1 use nice power-of-2 values! */
  452. ctrl->max_page_size = 16 * 1024;
  453. ctrl->max_block_size = 2 * 1024 * 1024;
  454. } else {
  455. ctrl->page_sizes = page_sizes;
  456. if (ctrl->nand_version >= 0x0600)
  457. ctrl->block_sizes = block_sizes_v6;
  458. else
  459. ctrl->block_sizes = block_sizes_v4;
  460. if (ctrl->nand_version < 0x0400) {
  461. ctrl->max_page_size = 4096;
  462. ctrl->max_block_size = 512 * 1024;
  463. }
  464. }
  465. /* Maximum spare area sector size (per 512B) */
  466. if (ctrl->nand_version >= 0x0702)
  467. ctrl->max_oob = 128;
  468. else if (ctrl->nand_version >= 0x0600)
  469. ctrl->max_oob = 64;
  470. else if (ctrl->nand_version >= 0x0500)
  471. ctrl->max_oob = 32;
  472. else
  473. ctrl->max_oob = 16;
  474. /* v6.0 and newer (except v6.1) have prefetch support */
  475. if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
  476. ctrl->features |= BRCMNAND_HAS_PREFETCH;
  477. /*
  478. * v6.x has cache mode, but it's implemented differently. Ignore it for
  479. * now.
  480. */
  481. if (ctrl->nand_version >= 0x0700)
  482. ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
  483. if (ctrl->nand_version >= 0x0500)
  484. ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
  485. if (ctrl->nand_version >= 0x0700)
  486. ctrl->features |= BRCMNAND_HAS_WP;
  487. #ifndef __UBOOT__
  488. else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
  489. #else
  490. else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp"))
  491. #endif /* __UBOOT__ */
  492. ctrl->features |= BRCMNAND_HAS_WP;
  493. return 0;
  494. }
  495. static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
  496. enum brcmnand_reg reg)
  497. {
  498. u16 offs = ctrl->reg_offsets[reg];
  499. if (offs)
  500. return nand_readreg(ctrl, offs);
  501. else
  502. return 0;
  503. }
  504. static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
  505. enum brcmnand_reg reg, u32 val)
  506. {
  507. u16 offs = ctrl->reg_offsets[reg];
  508. if (offs)
  509. nand_writereg(ctrl, offs, val);
  510. }
  511. static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
  512. enum brcmnand_reg reg, u32 mask, unsigned
  513. int shift, u32 val)
  514. {
  515. u32 tmp = brcmnand_read_reg(ctrl, reg);
  516. tmp &= ~mask;
  517. tmp |= val << shift;
  518. brcmnand_write_reg(ctrl, reg, tmp);
  519. }
  520. static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
  521. {
  522. return __raw_readl(ctrl->nand_fc + word * 4);
  523. }
  524. static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
  525. int word, u32 val)
  526. {
  527. __raw_writel(val, ctrl->nand_fc + word * 4);
  528. }
  529. static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
  530. enum brcmnand_cs_reg reg)
  531. {
  532. u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
  533. u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
  534. u8 cs_offs;
  535. if (cs == 0 && ctrl->cs0_offsets)
  536. cs_offs = ctrl->cs0_offsets[reg];
  537. else
  538. cs_offs = ctrl->cs_offsets[reg];
  539. if (cs && offs_cs1)
  540. return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
  541. return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
  542. }
  543. static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
  544. {
  545. if (ctrl->nand_version < 0x0600)
  546. return 1;
  547. return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
  548. }
  549. static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
  550. {
  551. struct brcmnand_controller *ctrl = host->ctrl;
  552. unsigned int shift = 0, bits;
  553. enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
  554. int cs = host->cs;
  555. if (ctrl->nand_version >= 0x0702)
  556. bits = 7;
  557. else if (ctrl->nand_version >= 0x0600)
  558. bits = 6;
  559. else if (ctrl->nand_version >= 0x0500)
  560. bits = 5;
  561. else
  562. bits = 4;
  563. if (ctrl->nand_version >= 0x0702) {
  564. if (cs >= 4)
  565. reg = BRCMNAND_CORR_THRESHOLD_EXT;
  566. shift = (cs % 4) * bits;
  567. } else if (ctrl->nand_version >= 0x0600) {
  568. if (cs >= 5)
  569. reg = BRCMNAND_CORR_THRESHOLD_EXT;
  570. shift = (cs % 5) * bits;
  571. }
  572. brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
  573. }
  574. static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
  575. {
  576. if (ctrl->nand_version < 0x0602)
  577. return 24;
  578. return 0;
  579. }
  580. /***********************************************************************
  581. * NAND ACC CONTROL bitfield
  582. *
  583. * Some bits have remained constant throughout hardware revision, while
  584. * others have shifted around.
  585. ***********************************************************************/
  586. /* Constant for all versions (where supported) */
  587. enum {
  588. /* See BRCMNAND_HAS_CACHE_MODE */
  589. ACC_CONTROL_CACHE_MODE = BIT(22),
  590. /* See BRCMNAND_HAS_PREFETCH */
  591. ACC_CONTROL_PREFETCH = BIT(23),
  592. ACC_CONTROL_PAGE_HIT = BIT(24),
  593. ACC_CONTROL_WR_PREEMPT = BIT(25),
  594. ACC_CONTROL_PARTIAL_PAGE = BIT(26),
  595. ACC_CONTROL_RD_ERASED = BIT(27),
  596. ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
  597. ACC_CONTROL_WR_ECC = BIT(30),
  598. ACC_CONTROL_RD_ECC = BIT(31),
  599. };
  600. static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
  601. {
  602. if (ctrl->nand_version >= 0x0702)
  603. return GENMASK(7, 0);
  604. else if (ctrl->nand_version >= 0x0600)
  605. return GENMASK(6, 0);
  606. else
  607. return GENMASK(5, 0);
  608. }
  609. #define NAND_ACC_CONTROL_ECC_SHIFT 16
  610. #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
  611. static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
  612. {
  613. u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
  614. mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
  615. /* v7.2 includes additional ECC levels */
  616. if (ctrl->nand_version >= 0x0702)
  617. mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
  618. return mask;
  619. }
  620. static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
  621. {
  622. struct brcmnand_controller *ctrl = host->ctrl;
  623. u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
  624. u32 acc_control = nand_readreg(ctrl, offs);
  625. u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
  626. if (en) {
  627. acc_control |= ecc_flags; /* enable RD/WR ECC */
  628. acc_control |= host->hwcfg.ecc_level
  629. << NAND_ACC_CONTROL_ECC_SHIFT;
  630. } else {
  631. acc_control &= ~ecc_flags; /* disable RD/WR ECC */
  632. acc_control &= ~brcmnand_ecc_level_mask(ctrl);
  633. }
  634. nand_writereg(ctrl, offs, acc_control);
  635. }
  636. static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
  637. {
  638. if (ctrl->nand_version >= 0x0702)
  639. return 9;
  640. else if (ctrl->nand_version >= 0x0600)
  641. return 7;
  642. else if (ctrl->nand_version >= 0x0500)
  643. return 6;
  644. else
  645. return -1;
  646. }
  647. static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
  648. {
  649. struct brcmnand_controller *ctrl = host->ctrl;
  650. int shift = brcmnand_sector_1k_shift(ctrl);
  651. u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
  652. BRCMNAND_CS_ACC_CONTROL);
  653. if (shift < 0)
  654. return 0;
  655. return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
  656. }
  657. static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
  658. {
  659. struct brcmnand_controller *ctrl = host->ctrl;
  660. int shift = brcmnand_sector_1k_shift(ctrl);
  661. u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
  662. BRCMNAND_CS_ACC_CONTROL);
  663. u32 tmp;
  664. if (shift < 0)
  665. return;
  666. tmp = nand_readreg(ctrl, acc_control_offs);
  667. tmp &= ~(1 << shift);
  668. tmp |= (!!val) << shift;
  669. nand_writereg(ctrl, acc_control_offs, tmp);
  670. }
  671. /***********************************************************************
  672. * CS_NAND_SELECT
  673. ***********************************************************************/
  674. enum {
  675. CS_SELECT_NAND_WP = BIT(29),
  676. CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
  677. };
  678. static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
  679. u32 mask, u32 expected_val,
  680. unsigned long timeout_ms)
  681. {
  682. #ifndef __UBOOT__
  683. unsigned long limit;
  684. u32 val;
  685. if (!timeout_ms)
  686. timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
  687. limit = jiffies + msecs_to_jiffies(timeout_ms);
  688. do {
  689. val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
  690. if ((val & mask) == expected_val)
  691. return 0;
  692. cpu_relax();
  693. } while (time_after(limit, jiffies));
  694. #else
  695. unsigned long base, limit;
  696. u32 val;
  697. if (!timeout_ms)
  698. timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
  699. base = get_timer(0);
  700. limit = CONFIG_SYS_HZ * timeout_ms / 1000;
  701. do {
  702. val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
  703. if ((val & mask) == expected_val)
  704. return 0;
  705. cpu_relax();
  706. } while (get_timer(base) < limit);
  707. #endif /* __UBOOT__ */
  708. dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
  709. expected_val, val & mask);
  710. return -ETIMEDOUT;
  711. }
  712. static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
  713. {
  714. u32 val = en ? CS_SELECT_NAND_WP : 0;
  715. brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
  716. }
  717. /***********************************************************************
  718. * Flash DMA
  719. ***********************************************************************/
  720. enum flash_dma_reg {
  721. FLASH_DMA_REVISION = 0x00,
  722. FLASH_DMA_FIRST_DESC = 0x04,
  723. FLASH_DMA_FIRST_DESC_EXT = 0x08,
  724. FLASH_DMA_CTRL = 0x0c,
  725. FLASH_DMA_MODE = 0x10,
  726. FLASH_DMA_STATUS = 0x14,
  727. FLASH_DMA_INTERRUPT_DESC = 0x18,
  728. FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
  729. FLASH_DMA_ERROR_STATUS = 0x20,
  730. FLASH_DMA_CURRENT_DESC = 0x24,
  731. FLASH_DMA_CURRENT_DESC_EXT = 0x28,
  732. };
  733. static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
  734. {
  735. return ctrl->flash_dma_base;
  736. }
  737. static inline bool flash_dma_buf_ok(const void *buf)
  738. {
  739. #ifndef __UBOOT__
  740. return buf && !is_vmalloc_addr(buf) &&
  741. likely(IS_ALIGNED((uintptr_t)buf, 4));
  742. #else
  743. return buf && likely(IS_ALIGNED((uintptr_t)buf, 4));
  744. #endif /* __UBOOT__ */
  745. }
  746. static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
  747. u32 val)
  748. {
  749. brcmnand_writel(val, ctrl->flash_dma_base + offs);
  750. }
  751. static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
  752. {
  753. return brcmnand_readl(ctrl->flash_dma_base + offs);
  754. }
  755. /* Low-level operation types: command, address, write, or read */
  756. enum brcmnand_llop_type {
  757. LL_OP_CMD,
  758. LL_OP_ADDR,
  759. LL_OP_WR,
  760. LL_OP_RD,
  761. };
  762. /***********************************************************************
  763. * Internal support functions
  764. ***********************************************************************/
  765. static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
  766. struct brcmnand_cfg *cfg)
  767. {
  768. if (ctrl->nand_version <= 0x0701)
  769. return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
  770. cfg->ecc_level == 15;
  771. else
  772. return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
  773. cfg->ecc_level == 15) ||
  774. (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
  775. }
  776. /*
  777. * Returns a nand_ecclayout strucutre for the given layout/configuration.
  778. * Returns NULL on failure.
  779. */
  780. static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
  781. struct brcmnand_host *host)
  782. {
  783. struct brcmnand_cfg *cfg = &host->hwcfg;
  784. int i, j;
  785. struct nand_ecclayout *layout;
  786. int req;
  787. int sectors;
  788. int sas;
  789. int idx1, idx2;
  790. #ifndef __UBOOT__
  791. layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
  792. #else
  793. layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL);
  794. #endif
  795. if (!layout)
  796. return NULL;
  797. sectors = cfg->page_size / (512 << cfg->sector_size_1k);
  798. sas = cfg->spare_area_size << cfg->sector_size_1k;
  799. /* Hamming */
  800. if (is_hamming_ecc(host->ctrl, cfg)) {
  801. for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
  802. /* First sector of each page may have BBI */
  803. if (i == 0) {
  804. layout->oobfree[idx2].offset = i * sas + 1;
  805. /* Small-page NAND use byte 6 for BBI */
  806. if (cfg->page_size == 512)
  807. layout->oobfree[idx2].offset--;
  808. layout->oobfree[idx2].length = 5;
  809. } else {
  810. layout->oobfree[idx2].offset = i * sas;
  811. layout->oobfree[idx2].length = 6;
  812. }
  813. idx2++;
  814. layout->eccpos[idx1++] = i * sas + 6;
  815. layout->eccpos[idx1++] = i * sas + 7;
  816. layout->eccpos[idx1++] = i * sas + 8;
  817. layout->oobfree[idx2].offset = i * sas + 9;
  818. layout->oobfree[idx2].length = 7;
  819. idx2++;
  820. /* Leave zero-terminated entry for OOBFREE */
  821. if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
  822. idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
  823. break;
  824. }
  825. return layout;
  826. }
  827. /*
  828. * CONTROLLER_VERSION:
  829. * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
  830. * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
  831. * But we will just be conservative.
  832. */
  833. req = DIV_ROUND_UP(ecc_level * 14, 8);
  834. if (req >= sas) {
  835. dev_err(&host->pdev->dev,
  836. "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
  837. req, sas);
  838. return NULL;
  839. }
  840. layout->eccbytes = req * sectors;
  841. for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
  842. for (j = sas - req; j < sas && idx1 <
  843. MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
  844. layout->eccpos[idx1] = i * sas + j;
  845. /* First sector of each page may have BBI */
  846. if (i == 0) {
  847. if (cfg->page_size == 512 && (sas - req >= 6)) {
  848. /* Small-page NAND use byte 6 for BBI */
  849. layout->oobfree[idx2].offset = 0;
  850. layout->oobfree[idx2].length = 5;
  851. idx2++;
  852. if (sas - req > 6) {
  853. layout->oobfree[idx2].offset = 6;
  854. layout->oobfree[idx2].length =
  855. sas - req - 6;
  856. idx2++;
  857. }
  858. } else if (sas > req + 1) {
  859. layout->oobfree[idx2].offset = i * sas + 1;
  860. layout->oobfree[idx2].length = sas - req - 1;
  861. idx2++;
  862. }
  863. } else if (sas > req) {
  864. layout->oobfree[idx2].offset = i * sas;
  865. layout->oobfree[idx2].length = sas - req;
  866. idx2++;
  867. }
  868. /* Leave zero-terminated entry for OOBFREE */
  869. if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
  870. idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
  871. break;
  872. }
  873. return layout;
  874. }
  875. static struct nand_ecclayout *brcmstb_choose_ecc_layout(
  876. struct brcmnand_host *host)
  877. {
  878. struct nand_ecclayout *layout;
  879. struct brcmnand_cfg *p = &host->hwcfg;
  880. unsigned int ecc_level = p->ecc_level;
  881. if (p->sector_size_1k)
  882. ecc_level <<= 1;
  883. layout = brcmnand_create_layout(ecc_level, host);
  884. if (!layout) {
  885. dev_err(&host->pdev->dev,
  886. "no proper ecc_layout for this NAND cfg\n");
  887. return NULL;
  888. }
  889. return layout;
  890. }
  891. static void brcmnand_wp(struct mtd_info *mtd, int wp)
  892. {
  893. struct nand_chip *chip = mtd_to_nand(mtd);
  894. struct brcmnand_host *host = nand_get_controller_data(chip);
  895. struct brcmnand_controller *ctrl = host->ctrl;
  896. if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
  897. static int old_wp = -1;
  898. int ret;
  899. if (old_wp != wp) {
  900. dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
  901. old_wp = wp;
  902. }
  903. /*
  904. * make sure ctrl/flash ready before and after
  905. * changing state of #WP pin
  906. */
  907. ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
  908. NAND_STATUS_READY,
  909. NAND_CTRL_RDY |
  910. NAND_STATUS_READY, 0);
  911. if (ret)
  912. return;
  913. brcmnand_set_wp(ctrl, wp);
  914. nand_status_op(chip, NULL);
  915. /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
  916. ret = bcmnand_ctrl_poll_status(ctrl,
  917. NAND_CTRL_RDY |
  918. NAND_STATUS_READY |
  919. NAND_STATUS_WP,
  920. NAND_CTRL_RDY |
  921. NAND_STATUS_READY |
  922. (wp ? 0 : NAND_STATUS_WP), 0);
  923. #ifndef __UBOOT__
  924. if (ret)
  925. dev_err_ratelimited(&host->pdev->dev,
  926. "nand #WP expected %s\n",
  927. wp ? "on" : "off");
  928. #else
  929. if (ret)
  930. dev_err(&host->pdev->dev,
  931. "nand #WP expected %s\n",
  932. wp ? "on" : "off");
  933. #endif /* __UBOOT__ */
  934. }
  935. }
  936. /* Helper functions for reading and writing OOB registers */
  937. static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
  938. {
  939. u16 offset0, offset10, reg_offs;
  940. offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
  941. offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
  942. if (offs >= ctrl->max_oob)
  943. return 0x77;
  944. if (offs >= 16 && offset10)
  945. reg_offs = offset10 + ((offs - 0x10) & ~0x03);
  946. else
  947. reg_offs = offset0 + (offs & ~0x03);
  948. return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
  949. }
  950. static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
  951. u32 data)
  952. {
  953. u16 offset0, offset10, reg_offs;
  954. offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
  955. offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
  956. if (offs >= ctrl->max_oob)
  957. return;
  958. if (offs >= 16 && offset10)
  959. reg_offs = offset10 + ((offs - 0x10) & ~0x03);
  960. else
  961. reg_offs = offset0 + (offs & ~0x03);
  962. nand_writereg(ctrl, reg_offs, data);
  963. }
  964. /*
  965. * read_oob_from_regs - read data from OOB registers
  966. * @ctrl: NAND controller
  967. * @i: sub-page sector index
  968. * @oob: buffer to read to
  969. * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
  970. * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
  971. */
  972. static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
  973. int sas, int sector_1k)
  974. {
  975. int tbytes = sas << sector_1k;
  976. int j;
  977. /* Adjust OOB values for 1K sector size */
  978. if (sector_1k && (i & 0x01))
  979. tbytes = max(0, tbytes - (int)ctrl->max_oob);
  980. tbytes = min_t(int, tbytes, ctrl->max_oob);
  981. for (j = 0; j < tbytes; j++)
  982. oob[j] = oob_reg_read(ctrl, j);
  983. return tbytes;
  984. }
  985. /*
  986. * write_oob_to_regs - write data to OOB registers
  987. * @i: sub-page sector index
  988. * @oob: buffer to write from
  989. * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
  990. * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
  991. */
  992. static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
  993. const u8 *oob, int sas, int sector_1k)
  994. {
  995. int tbytes = sas << sector_1k;
  996. int j;
  997. /* Adjust OOB values for 1K sector size */
  998. if (sector_1k && (i & 0x01))
  999. tbytes = max(0, tbytes - (int)ctrl->max_oob);
  1000. tbytes = min_t(int, tbytes, ctrl->max_oob);
  1001. for (j = 0; j < tbytes; j += 4)
  1002. oob_reg_write(ctrl, j,
  1003. (oob[j + 0] << 24) |
  1004. (oob[j + 1] << 16) |
  1005. (oob[j + 2] << 8) |
  1006. (oob[j + 3] << 0));
  1007. return tbytes;
  1008. }
  1009. #ifndef __UBOOT__
  1010. static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
  1011. {
  1012. struct brcmnand_controller *ctrl = data;
  1013. /* Discard all NAND_CTLRDY interrupts during DMA */
  1014. if (ctrl->dma_pending)
  1015. return IRQ_HANDLED;
  1016. complete(&ctrl->done);
  1017. return IRQ_HANDLED;
  1018. }
  1019. /* Handle SoC-specific interrupt hardware */
  1020. static irqreturn_t brcmnand_irq(int irq, void *data)
  1021. {
  1022. struct brcmnand_controller *ctrl = data;
  1023. if (ctrl->soc->ctlrdy_ack(ctrl->soc))
  1024. return brcmnand_ctlrdy_irq(irq, data);
  1025. return IRQ_NONE;
  1026. }
  1027. static irqreturn_t brcmnand_dma_irq(int irq, void *data)
  1028. {
  1029. struct brcmnand_controller *ctrl = data;
  1030. complete(&ctrl->dma_done);
  1031. return IRQ_HANDLED;
  1032. }
  1033. #endif /* __UBOOT__ */
  1034. static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
  1035. {
  1036. struct brcmnand_controller *ctrl = host->ctrl;
  1037. int ret;
  1038. dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
  1039. brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
  1040. BUG_ON(ctrl->cmd_pending != 0);
  1041. ctrl->cmd_pending = cmd;
  1042. ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
  1043. WARN_ON(ret);
  1044. mb(); /* flush previous writes */
  1045. brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
  1046. cmd << brcmnand_cmd_shift(ctrl));
  1047. }
  1048. /***********************************************************************
  1049. * NAND MTD API: read/program/erase
  1050. ***********************************************************************/
  1051. static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
  1052. unsigned int ctrl)
  1053. {
  1054. /* intentionally left blank */
  1055. }
  1056. static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1057. {
  1058. struct nand_chip *chip = mtd_to_nand(mtd);
  1059. struct brcmnand_host *host = nand_get_controller_data(chip);
  1060. struct brcmnand_controller *ctrl = host->ctrl;
  1061. #ifndef __UBOOT__
  1062. unsigned long timeo = msecs_to_jiffies(100);
  1063. dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
  1064. if (ctrl->cmd_pending &&
  1065. wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
  1066. u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
  1067. >> brcmnand_cmd_shift(ctrl);
  1068. dev_err_ratelimited(ctrl->dev,
  1069. "timeout waiting for command %#02x\n", cmd);
  1070. dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
  1071. brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
  1072. }
  1073. #else
  1074. unsigned long timeo = 100; /* 100 msec */
  1075. int ret;
  1076. dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
  1077. ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo);
  1078. WARN_ON(ret);
  1079. #endif /* __UBOOT__ */
  1080. ctrl->cmd_pending = 0;
  1081. return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
  1082. INTFC_FLASH_STATUS;
  1083. }
  1084. enum {
  1085. LLOP_RE = BIT(16),
  1086. LLOP_WE = BIT(17),
  1087. LLOP_ALE = BIT(18),
  1088. LLOP_CLE = BIT(19),
  1089. LLOP_RETURN_IDLE = BIT(31),
  1090. LLOP_DATA_MASK = GENMASK(15, 0),
  1091. };
  1092. static int brcmnand_low_level_op(struct brcmnand_host *host,
  1093. enum brcmnand_llop_type type, u32 data,
  1094. bool last_op)
  1095. {
  1096. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  1097. struct nand_chip *chip = &host->chip;
  1098. struct brcmnand_controller *ctrl = host->ctrl;
  1099. u32 tmp;
  1100. tmp = data & LLOP_DATA_MASK;
  1101. switch (type) {
  1102. case LL_OP_CMD:
  1103. tmp |= LLOP_WE | LLOP_CLE;
  1104. break;
  1105. case LL_OP_ADDR:
  1106. /* WE | ALE */
  1107. tmp |= LLOP_WE | LLOP_ALE;
  1108. break;
  1109. case LL_OP_WR:
  1110. /* WE */
  1111. tmp |= LLOP_WE;
  1112. break;
  1113. case LL_OP_RD:
  1114. /* RE */
  1115. tmp |= LLOP_RE;
  1116. break;
  1117. }
  1118. if (last_op)
  1119. /* RETURN_IDLE */
  1120. tmp |= LLOP_RETURN_IDLE;
  1121. dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
  1122. brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
  1123. (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
  1124. brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
  1125. return brcmnand_waitfunc(mtd, chip);
  1126. }
  1127. static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
  1128. int column, int page_addr)
  1129. {
  1130. struct nand_chip *chip = mtd_to_nand(mtd);
  1131. struct brcmnand_host *host = nand_get_controller_data(chip);
  1132. struct brcmnand_controller *ctrl = host->ctrl;
  1133. u64 addr = (u64)page_addr << chip->page_shift;
  1134. int native_cmd = 0;
  1135. if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
  1136. command == NAND_CMD_RNDOUT)
  1137. addr = (u64)column;
  1138. /* Avoid propagating a negative, don't-care address */
  1139. else if (page_addr < 0)
  1140. addr = 0;
  1141. dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
  1142. (unsigned long long)addr);
  1143. host->last_cmd = command;
  1144. host->last_byte = 0;
  1145. host->last_addr = addr;
  1146. switch (command) {
  1147. case NAND_CMD_RESET:
  1148. native_cmd = CMD_FLASH_RESET;
  1149. break;
  1150. case NAND_CMD_STATUS:
  1151. native_cmd = CMD_STATUS_READ;
  1152. break;
  1153. case NAND_CMD_READID:
  1154. native_cmd = CMD_DEVICE_ID_READ;
  1155. break;
  1156. case NAND_CMD_READOOB:
  1157. native_cmd = CMD_SPARE_AREA_READ;
  1158. break;
  1159. case NAND_CMD_ERASE1:
  1160. native_cmd = CMD_BLOCK_ERASE;
  1161. brcmnand_wp(mtd, 0);
  1162. break;
  1163. case NAND_CMD_PARAM:
  1164. native_cmd = CMD_PARAMETER_READ;
  1165. break;
  1166. case NAND_CMD_SET_FEATURES:
  1167. case NAND_CMD_GET_FEATURES:
  1168. brcmnand_low_level_op(host, LL_OP_CMD, command, false);
  1169. brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
  1170. break;
  1171. case NAND_CMD_RNDOUT:
  1172. native_cmd = CMD_PARAMETER_CHANGE_COL;
  1173. addr &= ~((u64)(FC_BYTES - 1));
  1174. /*
  1175. * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
  1176. * NB: hwcfg.sector_size_1k may not be initialized yet
  1177. */
  1178. if (brcmnand_get_sector_size_1k(host)) {
  1179. host->hwcfg.sector_size_1k =
  1180. brcmnand_get_sector_size_1k(host);
  1181. brcmnand_set_sector_size_1k(host, 0);
  1182. }
  1183. break;
  1184. }
  1185. if (!native_cmd)
  1186. return;
  1187. brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
  1188. (host->cs << 16) | ((addr >> 32) & 0xffff));
  1189. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
  1190. brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
  1191. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
  1192. brcmnand_send_cmd(host, native_cmd);
  1193. brcmnand_waitfunc(mtd, chip);
  1194. if (native_cmd == CMD_PARAMETER_READ ||
  1195. native_cmd == CMD_PARAMETER_CHANGE_COL) {
  1196. /* Copy flash cache word-wise */
  1197. u32 *flash_cache = (u32 *)ctrl->flash_cache;
  1198. int i;
  1199. brcmnand_soc_data_bus_prepare(ctrl->soc, true);
  1200. /*
  1201. * Must cache the FLASH_CACHE now, since changes in
  1202. * SECTOR_SIZE_1K may invalidate it
  1203. */
  1204. for (i = 0; i < FC_WORDS; i++) {
  1205. u32 fc;
  1206. fc = brcmnand_read_fc(ctrl, i);
  1207. /*
  1208. * Flash cache is big endian for parameter pages, at
  1209. * least on STB SoCs
  1210. */
  1211. if (ctrl->parameter_page_big_endian)
  1212. flash_cache[i] = be32_to_cpu(fc);
  1213. else
  1214. flash_cache[i] = le32_to_cpu(fc);
  1215. }
  1216. brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
  1217. /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
  1218. if (host->hwcfg.sector_size_1k)
  1219. brcmnand_set_sector_size_1k(host,
  1220. host->hwcfg.sector_size_1k);
  1221. }
  1222. /* Re-enable protection is necessary only after erase */
  1223. if (command == NAND_CMD_ERASE1)
  1224. brcmnand_wp(mtd, 1);
  1225. }
  1226. static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
  1227. {
  1228. struct nand_chip *chip = mtd_to_nand(mtd);
  1229. struct brcmnand_host *host = nand_get_controller_data(chip);
  1230. struct brcmnand_controller *ctrl = host->ctrl;
  1231. uint8_t ret = 0;
  1232. int addr, offs;
  1233. switch (host->last_cmd) {
  1234. case NAND_CMD_READID:
  1235. if (host->last_byte < 4)
  1236. ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
  1237. (24 - (host->last_byte << 3));
  1238. else if (host->last_byte < 8)
  1239. ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
  1240. (56 - (host->last_byte << 3));
  1241. break;
  1242. case NAND_CMD_READOOB:
  1243. ret = oob_reg_read(ctrl, host->last_byte);
  1244. break;
  1245. case NAND_CMD_STATUS:
  1246. ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
  1247. INTFC_FLASH_STATUS;
  1248. if (wp_on) /* hide WP status */
  1249. ret |= NAND_STATUS_WP;
  1250. break;
  1251. case NAND_CMD_PARAM:
  1252. case NAND_CMD_RNDOUT:
  1253. addr = host->last_addr + host->last_byte;
  1254. offs = addr & (FC_BYTES - 1);
  1255. /* At FC_BYTES boundary, switch to next column */
  1256. if (host->last_byte > 0 && offs == 0)
  1257. nand_change_read_column_op(chip, addr, NULL, 0, false);
  1258. ret = ctrl->flash_cache[offs];
  1259. break;
  1260. case NAND_CMD_GET_FEATURES:
  1261. if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
  1262. ret = 0;
  1263. } else {
  1264. bool last = host->last_byte ==
  1265. ONFI_SUBFEATURE_PARAM_LEN - 1;
  1266. brcmnand_low_level_op(host, LL_OP_RD, 0, last);
  1267. ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
  1268. }
  1269. }
  1270. dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
  1271. host->last_byte++;
  1272. return ret;
  1273. }
  1274. static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1275. {
  1276. int i;
  1277. for (i = 0; i < len; i++, buf++)
  1278. *buf = brcmnand_read_byte(mtd);
  1279. }
  1280. static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  1281. int len)
  1282. {
  1283. int i;
  1284. struct nand_chip *chip = mtd_to_nand(mtd);
  1285. struct brcmnand_host *host = nand_get_controller_data(chip);
  1286. switch (host->last_cmd) {
  1287. case NAND_CMD_SET_FEATURES:
  1288. for (i = 0; i < len; i++)
  1289. brcmnand_low_level_op(host, LL_OP_WR, buf[i],
  1290. (i + 1) == len);
  1291. break;
  1292. default:
  1293. BUG();
  1294. break;
  1295. }
  1296. }
  1297. /**
  1298. * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
  1299. * following ahead of time:
  1300. * - Is this descriptor the beginning or end of a linked list?
  1301. * - What is the (DMA) address of the next descriptor in the linked list?
  1302. */
  1303. #ifndef __UBOOT__
  1304. static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
  1305. struct brcm_nand_dma_desc *desc, u64 addr,
  1306. dma_addr_t buf, u32 len, u8 dma_cmd,
  1307. bool begin, bool end,
  1308. dma_addr_t next_desc)
  1309. {
  1310. memset(desc, 0, sizeof(*desc));
  1311. /* Descriptors are written in native byte order (wordwise) */
  1312. desc->next_desc = lower_32_bits(next_desc);
  1313. desc->next_desc_ext = upper_32_bits(next_desc);
  1314. desc->cmd_irq = (dma_cmd << 24) |
  1315. (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
  1316. (!!begin) | ((!!end) << 1); /* head, tail */
  1317. #ifdef CONFIG_CPU_BIG_ENDIAN
  1318. desc->cmd_irq |= 0x01 << 12;
  1319. #endif
  1320. desc->dram_addr = lower_32_bits(buf);
  1321. desc->dram_addr_ext = upper_32_bits(buf);
  1322. desc->tfr_len = len;
  1323. desc->total_len = len;
  1324. desc->flash_addr = lower_32_bits(addr);
  1325. desc->flash_addr_ext = upper_32_bits(addr);
  1326. desc->cs = host->cs;
  1327. desc->status_valid = 0x01;
  1328. return 0;
  1329. }
  1330. /**
  1331. * Kick the FLASH_DMA engine, with a given DMA descriptor
  1332. */
  1333. static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
  1334. {
  1335. struct brcmnand_controller *ctrl = host->ctrl;
  1336. unsigned long timeo = msecs_to_jiffies(100);
  1337. flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
  1338. (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
  1339. flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
  1340. (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
  1341. /* Start FLASH_DMA engine */
  1342. ctrl->dma_pending = true;
  1343. mb(); /* flush previous writes */
  1344. flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
  1345. if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
  1346. dev_err(ctrl->dev,
  1347. "timeout waiting for DMA; status %#x, error status %#x\n",
  1348. flash_dma_readl(ctrl, FLASH_DMA_STATUS),
  1349. flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
  1350. }
  1351. ctrl->dma_pending = false;
  1352. flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
  1353. }
  1354. static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
  1355. u32 len, u8 dma_cmd)
  1356. {
  1357. struct brcmnand_controller *ctrl = host->ctrl;
  1358. dma_addr_t buf_pa;
  1359. int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  1360. buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
  1361. if (dma_mapping_error(ctrl->dev, buf_pa)) {
  1362. dev_err(ctrl->dev, "unable to map buffer for DMA\n");
  1363. return -ENOMEM;
  1364. }
  1365. brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
  1366. dma_cmd, true, true, 0);
  1367. brcmnand_dma_run(host, ctrl->dma_pa);
  1368. dma_unmap_single(ctrl->dev, buf_pa, len, dir);
  1369. if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
  1370. return -EBADMSG;
  1371. else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
  1372. return -EUCLEAN;
  1373. return 0;
  1374. }
  1375. #endif /* __UBOOT__ */
  1376. /*
  1377. * Assumes proper CS is already set
  1378. */
  1379. static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
  1380. u64 addr, unsigned int trans, u32 *buf,
  1381. u8 *oob, u64 *err_addr)
  1382. {
  1383. struct brcmnand_host *host = nand_get_controller_data(chip);
  1384. struct brcmnand_controller *ctrl = host->ctrl;
  1385. int i, j, ret = 0;
  1386. /* Clear error addresses */
  1387. brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
  1388. brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
  1389. brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
  1390. brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
  1391. brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
  1392. (host->cs << 16) | ((addr >> 32) & 0xffff));
  1393. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
  1394. for (i = 0; i < trans; i++, addr += FC_BYTES) {
  1395. brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
  1396. lower_32_bits(addr));
  1397. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
  1398. /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
  1399. brcmnand_send_cmd(host, CMD_PAGE_READ);
  1400. brcmnand_waitfunc(mtd, chip);
  1401. if (likely(buf)) {
  1402. brcmnand_soc_data_bus_prepare(ctrl->soc, false);
  1403. for (j = 0; j < FC_WORDS; j++, buf++)
  1404. *buf = brcmnand_read_fc(ctrl, j);
  1405. brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
  1406. }
  1407. if (oob)
  1408. oob += read_oob_from_regs(ctrl, i, oob,
  1409. mtd->oobsize / trans,
  1410. host->hwcfg.sector_size_1k);
  1411. if (!ret) {
  1412. *err_addr = brcmnand_read_reg(ctrl,
  1413. BRCMNAND_UNCORR_ADDR) |
  1414. ((u64)(brcmnand_read_reg(ctrl,
  1415. BRCMNAND_UNCORR_EXT_ADDR)
  1416. & 0xffff) << 32);
  1417. if (*err_addr)
  1418. ret = -EBADMSG;
  1419. }
  1420. if (!ret) {
  1421. *err_addr = brcmnand_read_reg(ctrl,
  1422. BRCMNAND_CORR_ADDR) |
  1423. ((u64)(brcmnand_read_reg(ctrl,
  1424. BRCMNAND_CORR_EXT_ADDR)
  1425. & 0xffff) << 32);
  1426. if (*err_addr)
  1427. ret = -EUCLEAN;
  1428. }
  1429. }
  1430. return ret;
  1431. }
  1432. /*
  1433. * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
  1434. * error
  1435. *
  1436. * Because the HW ECC signals an ECC error if an erase paged has even a single
  1437. * bitflip, we must check each ECC error to see if it is actually an erased
  1438. * page with bitflips, not a truly corrupted page.
  1439. *
  1440. * On a real error, return a negative error code (-EBADMSG for ECC error), and
  1441. * buf will contain raw data.
  1442. * Otherwise, buf gets filled with 0xffs and return the maximum number of
  1443. * bitflips-per-ECC-sector to the caller.
  1444. *
  1445. */
  1446. static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
  1447. struct nand_chip *chip, void *buf, u64 addr)
  1448. {
  1449. int i, sas;
  1450. void *oob = chip->oob_poi;
  1451. int bitflips = 0;
  1452. int page = addr >> chip->page_shift;
  1453. int ret;
  1454. if (!buf) {
  1455. #ifndef __UBOOT__
  1456. buf = chip->data_buf;
  1457. #else
  1458. buf = chip->buffers->databuf;
  1459. #endif
  1460. /* Invalidate page cache */
  1461. chip->pagebuf = -1;
  1462. }
  1463. sas = mtd->oobsize / chip->ecc.steps;
  1464. /* read without ecc for verification */
  1465. ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
  1466. if (ret)
  1467. return ret;
  1468. for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
  1469. ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
  1470. oob, sas, NULL, 0,
  1471. chip->ecc.strength);
  1472. if (ret < 0)
  1473. return ret;
  1474. bitflips = max(bitflips, ret);
  1475. }
  1476. return bitflips;
  1477. }
  1478. static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
  1479. u64 addr, unsigned int trans, u32 *buf, u8 *oob)
  1480. {
  1481. struct brcmnand_host *host = nand_get_controller_data(chip);
  1482. struct brcmnand_controller *ctrl = host->ctrl;
  1483. u64 err_addr = 0;
  1484. int err;
  1485. bool retry = true;
  1486. dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
  1487. try_dmaread:
  1488. brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
  1489. #ifndef __UBOOT__
  1490. if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
  1491. err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
  1492. CMD_PAGE_READ);
  1493. if (err) {
  1494. if (mtd_is_bitflip_or_eccerr(err))
  1495. err_addr = addr;
  1496. else
  1497. return -EIO;
  1498. }
  1499. } else {
  1500. if (oob)
  1501. memset(oob, 0x99, mtd->oobsize);
  1502. err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
  1503. oob, &err_addr);
  1504. }
  1505. #else
  1506. if (oob)
  1507. memset(oob, 0x99, mtd->oobsize);
  1508. err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
  1509. oob, &err_addr);
  1510. #endif /* __UBOOT__ */
  1511. if (mtd_is_eccerr(err)) {
  1512. /*
  1513. * On controller version and 7.0, 7.1 , DMA read after a
  1514. * prior PIO read that reported uncorrectable error,
  1515. * the DMA engine captures this error following DMA read
  1516. * cleared only on subsequent DMA read, so just retry once
  1517. * to clear a possible false error reported for current DMA
  1518. * read
  1519. */
  1520. if ((ctrl->nand_version == 0x0700) ||
  1521. (ctrl->nand_version == 0x0701)) {
  1522. if (retry) {
  1523. retry = false;
  1524. goto try_dmaread;
  1525. }
  1526. }
  1527. /*
  1528. * Controller version 7.2 has hw encoder to detect erased page
  1529. * bitflips, apply sw verification for older controllers only
  1530. */
  1531. if (ctrl->nand_version < 0x0702) {
  1532. err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
  1533. addr);
  1534. /* erased page bitflips corrected */
  1535. if (err >= 0)
  1536. return err;
  1537. }
  1538. dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
  1539. (unsigned long long)err_addr);
  1540. mtd->ecc_stats.failed++;
  1541. /* NAND layer expects zero on ECC errors */
  1542. return 0;
  1543. }
  1544. if (mtd_is_bitflip(err)) {
  1545. unsigned int corrected = brcmnand_count_corrected(ctrl);
  1546. dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
  1547. (unsigned long long)err_addr);
  1548. mtd->ecc_stats.corrected += corrected;
  1549. /* Always exceed the software-imposed threshold */
  1550. return max(mtd->bitflip_threshold, corrected);
  1551. }
  1552. return 0;
  1553. }
  1554. static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  1555. uint8_t *buf, int oob_required, int page)
  1556. {
  1557. struct brcmnand_host *host = nand_get_controller_data(chip);
  1558. u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
  1559. nand_read_page_op(chip, page, 0, NULL, 0);
  1560. return brcmnand_read(mtd, chip, host->last_addr,
  1561. mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
  1562. }
  1563. static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1564. uint8_t *buf, int oob_required, int page)
  1565. {
  1566. struct brcmnand_host *host = nand_get_controller_data(chip);
  1567. u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
  1568. int ret;
  1569. nand_read_page_op(chip, page, 0, NULL, 0);
  1570. brcmnand_set_ecc_enabled(host, 0);
  1571. ret = brcmnand_read(mtd, chip, host->last_addr,
  1572. mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
  1573. brcmnand_set_ecc_enabled(host, 1);
  1574. return ret;
  1575. }
  1576. static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  1577. int page)
  1578. {
  1579. return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
  1580. mtd->writesize >> FC_SHIFT,
  1581. NULL, (u8 *)chip->oob_poi);
  1582. }
  1583. static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1584. int page)
  1585. {
  1586. struct brcmnand_host *host = nand_get_controller_data(chip);
  1587. brcmnand_set_ecc_enabled(host, 0);
  1588. brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
  1589. mtd->writesize >> FC_SHIFT,
  1590. NULL, (u8 *)chip->oob_poi);
  1591. brcmnand_set_ecc_enabled(host, 1);
  1592. return 0;
  1593. }
  1594. static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
  1595. u64 addr, const u32 *buf, u8 *oob)
  1596. {
  1597. struct brcmnand_host *host = nand_get_controller_data(chip);
  1598. struct brcmnand_controller *ctrl = host->ctrl;
  1599. unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
  1600. int status, ret = 0;
  1601. dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
  1602. if (unlikely((unsigned long)buf & 0x03)) {
  1603. dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
  1604. buf = (u32 *)((unsigned long)buf & ~0x03);
  1605. }
  1606. brcmnand_wp(mtd, 0);
  1607. for (i = 0; i < ctrl->max_oob; i += 4)
  1608. oob_reg_write(ctrl, i, 0xffffffff);
  1609. #ifndef __UBOOT__
  1610. if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
  1611. if (brcmnand_dma_trans(host, addr, (u32 *)buf,
  1612. mtd->writesize, CMD_PROGRAM_PAGE))
  1613. ret = -EIO;
  1614. goto out;
  1615. }
  1616. #endif /* __UBOOT__ */
  1617. brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
  1618. (host->cs << 16) | ((addr >> 32) & 0xffff));
  1619. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
  1620. for (i = 0; i < trans; i++, addr += FC_BYTES) {
  1621. /* full address MUST be set before populating FC */
  1622. brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
  1623. lower_32_bits(addr));
  1624. (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
  1625. if (buf) {
  1626. brcmnand_soc_data_bus_prepare(ctrl->soc, false);
  1627. for (j = 0; j < FC_WORDS; j++, buf++)
  1628. brcmnand_write_fc(ctrl, j, *buf);
  1629. brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
  1630. } else if (oob) {
  1631. for (j = 0; j < FC_WORDS; j++)
  1632. brcmnand_write_fc(ctrl, j, 0xffffffff);
  1633. }
  1634. if (oob) {
  1635. oob += write_oob_to_regs(ctrl, i, oob,
  1636. mtd->oobsize / trans,
  1637. host->hwcfg.sector_size_1k);
  1638. }
  1639. /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
  1640. brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
  1641. status = brcmnand_waitfunc(mtd, chip);
  1642. if (status & NAND_STATUS_FAIL) {
  1643. dev_info(ctrl->dev, "program failed at %llx\n",
  1644. (unsigned long long)addr);
  1645. ret = -EIO;
  1646. goto out;
  1647. }
  1648. }
  1649. out:
  1650. brcmnand_wp(mtd, 1);
  1651. return ret;
  1652. }
  1653. static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  1654. const uint8_t *buf, int oob_required, int page)
  1655. {
  1656. struct brcmnand_host *host = nand_get_controller_data(chip);
  1657. void *oob = oob_required ? chip->oob_poi : NULL;
  1658. nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  1659. brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
  1660. return nand_prog_page_end_op(chip);
  1661. }
  1662. static int brcmnand_write_page_raw(struct mtd_info *mtd,
  1663. struct nand_chip *chip, const uint8_t *buf,
  1664. int oob_required, int page)
  1665. {
  1666. struct brcmnand_host *host = nand_get_controller_data(chip);
  1667. void *oob = oob_required ? chip->oob_poi : NULL;
  1668. nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  1669. brcmnand_set_ecc_enabled(host, 0);
  1670. brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
  1671. brcmnand_set_ecc_enabled(host, 1);
  1672. return nand_prog_page_end_op(chip);
  1673. }
  1674. static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  1675. int page)
  1676. {
  1677. return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
  1678. NULL, chip->oob_poi);
  1679. }
  1680. static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1681. int page)
  1682. {
  1683. struct brcmnand_host *host = nand_get_controller_data(chip);
  1684. int ret;
  1685. brcmnand_set_ecc_enabled(host, 0);
  1686. ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
  1687. (u8 *)chip->oob_poi);
  1688. brcmnand_set_ecc_enabled(host, 1);
  1689. return ret;
  1690. }
  1691. /***********************************************************************
  1692. * Per-CS setup (1 NAND device)
  1693. ***********************************************************************/
  1694. static int brcmnand_set_cfg(struct brcmnand_host *host,
  1695. struct brcmnand_cfg *cfg)
  1696. {
  1697. struct brcmnand_controller *ctrl = host->ctrl;
  1698. struct nand_chip *chip = &host->chip;
  1699. u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
  1700. u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
  1701. BRCMNAND_CS_CFG_EXT);
  1702. u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
  1703. BRCMNAND_CS_ACC_CONTROL);
  1704. u8 block_size = 0, page_size = 0, device_size = 0;
  1705. u32 tmp;
  1706. if (ctrl->block_sizes) {
  1707. int i, found;
  1708. for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
  1709. if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
  1710. block_size = i;
  1711. found = 1;
  1712. }
  1713. if (!found) {
  1714. dev_warn(ctrl->dev, "invalid block size %u\n",
  1715. cfg->block_size);
  1716. return -EINVAL;
  1717. }
  1718. } else {
  1719. block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
  1720. }
  1721. if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
  1722. cfg->block_size > ctrl->max_block_size)) {
  1723. dev_warn(ctrl->dev, "invalid block size %u\n",
  1724. cfg->block_size);
  1725. block_size = 0;
  1726. }
  1727. if (ctrl->page_sizes) {
  1728. int i, found;
  1729. for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
  1730. if (ctrl->page_sizes[i] == cfg->page_size) {
  1731. page_size = i;
  1732. found = 1;
  1733. }
  1734. if (!found) {
  1735. dev_warn(ctrl->dev, "invalid page size %u\n",
  1736. cfg->page_size);
  1737. return -EINVAL;
  1738. }
  1739. } else {
  1740. page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
  1741. }
  1742. if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
  1743. cfg->page_size > ctrl->max_page_size)) {
  1744. dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
  1745. return -EINVAL;
  1746. }
  1747. if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
  1748. dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
  1749. (unsigned long long)cfg->device_size);
  1750. return -EINVAL;
  1751. }
  1752. device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
  1753. tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
  1754. (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
  1755. (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
  1756. (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
  1757. (device_size << CFG_DEVICE_SIZE_SHIFT);
  1758. if (cfg_offs == cfg_ext_offs) {
  1759. tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
  1760. (block_size << CFG_BLK_SIZE_SHIFT);
  1761. nand_writereg(ctrl, cfg_offs, tmp);
  1762. } else {
  1763. nand_writereg(ctrl, cfg_offs, tmp);
  1764. tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
  1765. (block_size << CFG_EXT_BLK_SIZE_SHIFT);
  1766. nand_writereg(ctrl, cfg_ext_offs, tmp);
  1767. }
  1768. tmp = nand_readreg(ctrl, acc_control_offs);
  1769. tmp &= ~brcmnand_ecc_level_mask(ctrl);
  1770. tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
  1771. tmp &= ~brcmnand_spare_area_mask(ctrl);
  1772. tmp |= cfg->spare_area_size;
  1773. nand_writereg(ctrl, acc_control_offs, tmp);
  1774. brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
  1775. /* threshold = ceil(BCH-level * 0.75) */
  1776. brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
  1777. return 0;
  1778. }
  1779. static void brcmnand_print_cfg(struct brcmnand_host *host,
  1780. char *buf, struct brcmnand_cfg *cfg)
  1781. {
  1782. buf += sprintf(buf,
  1783. "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
  1784. (unsigned long long)cfg->device_size >> 20,
  1785. cfg->block_size >> 10,
  1786. cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
  1787. cfg->page_size >= 1024 ? "KiB" : "B",
  1788. cfg->spare_area_size, cfg->device_width);
  1789. /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
  1790. if (is_hamming_ecc(host->ctrl, cfg))
  1791. sprintf(buf, ", Hamming ECC");
  1792. else if (cfg->sector_size_1k)
  1793. sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
  1794. else
  1795. sprintf(buf, ", BCH-%u", cfg->ecc_level);
  1796. }
  1797. /*
  1798. * Minimum number of bytes to address a page. Calculated as:
  1799. * roundup(log2(size / page-size) / 8)
  1800. *
  1801. * NB: the following does not "round up" for non-power-of-2 'size'; but this is
  1802. * OK because many other things will break if 'size' is irregular...
  1803. */
  1804. static inline int get_blk_adr_bytes(u64 size, u32 writesize)
  1805. {
  1806. return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
  1807. }
  1808. static int brcmnand_setup_dev(struct brcmnand_host *host)
  1809. {
  1810. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  1811. struct nand_chip *chip = &host->chip;
  1812. struct brcmnand_controller *ctrl = host->ctrl;
  1813. struct brcmnand_cfg *cfg = &host->hwcfg;
  1814. char msg[128];
  1815. u32 offs, tmp, oob_sector;
  1816. int ret;
  1817. memset(cfg, 0, sizeof(*cfg));
  1818. #ifndef __UBOOT__
  1819. ret = of_property_read_u32(nand_get_flash_node(chip),
  1820. "brcm,nand-oob-sector-size",
  1821. &oob_sector);
  1822. #else
  1823. ret = ofnode_read_u32(nand_get_flash_node(chip),
  1824. "brcm,nand-oob-sector-size",
  1825. &oob_sector);
  1826. #endif /* __UBOOT__ */
  1827. if (ret) {
  1828. /* Use detected size */
  1829. cfg->spare_area_size = mtd->oobsize /
  1830. (mtd->writesize >> FC_SHIFT);
  1831. } else {
  1832. cfg->spare_area_size = oob_sector;
  1833. }
  1834. if (cfg->spare_area_size > ctrl->max_oob)
  1835. cfg->spare_area_size = ctrl->max_oob;
  1836. /*
  1837. * Set oobsize to be consistent with controller's spare_area_size, as
  1838. * the rest is inaccessible.
  1839. */
  1840. mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
  1841. cfg->device_size = mtd->size;
  1842. cfg->block_size = mtd->erasesize;
  1843. cfg->page_size = mtd->writesize;
  1844. cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
  1845. cfg->col_adr_bytes = 2;
  1846. cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
  1847. if (chip->ecc.mode != NAND_ECC_HW) {
  1848. dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
  1849. chip->ecc.mode);
  1850. return -EINVAL;
  1851. }
  1852. if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
  1853. if (chip->ecc.strength == 1 && chip->ecc.size == 512)
  1854. /* Default to Hamming for 1-bit ECC, if unspecified */
  1855. chip->ecc.algo = NAND_ECC_HAMMING;
  1856. else
  1857. /* Otherwise, BCH */
  1858. chip->ecc.algo = NAND_ECC_BCH;
  1859. }
  1860. if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
  1861. chip->ecc.size != 512)) {
  1862. dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
  1863. chip->ecc.strength, chip->ecc.size);
  1864. return -EINVAL;
  1865. }
  1866. switch (chip->ecc.size) {
  1867. case 512:
  1868. if (chip->ecc.algo == NAND_ECC_HAMMING)
  1869. cfg->ecc_level = 15;
  1870. else
  1871. cfg->ecc_level = chip->ecc.strength;
  1872. cfg->sector_size_1k = 0;
  1873. break;
  1874. case 1024:
  1875. if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
  1876. dev_err(ctrl->dev, "1KB sectors not supported\n");
  1877. return -EINVAL;
  1878. }
  1879. if (chip->ecc.strength & 0x1) {
  1880. dev_err(ctrl->dev,
  1881. "odd ECC not supported with 1KB sectors\n");
  1882. return -EINVAL;
  1883. }
  1884. cfg->ecc_level = chip->ecc.strength >> 1;
  1885. cfg->sector_size_1k = 1;
  1886. break;
  1887. default:
  1888. dev_err(ctrl->dev, "unsupported ECC size: %d\n",
  1889. chip->ecc.size);
  1890. return -EINVAL;
  1891. }
  1892. cfg->ful_adr_bytes = cfg->blk_adr_bytes;
  1893. if (mtd->writesize > 512)
  1894. cfg->ful_adr_bytes += cfg->col_adr_bytes;
  1895. else
  1896. cfg->ful_adr_bytes += 1;
  1897. ret = brcmnand_set_cfg(host, cfg);
  1898. if (ret)
  1899. return ret;
  1900. brcmnand_set_ecc_enabled(host, 1);
  1901. brcmnand_print_cfg(host, msg, cfg);
  1902. dev_info(ctrl->dev, "detected %s\n", msg);
  1903. /* Configure ACC_CONTROL */
  1904. offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
  1905. tmp = nand_readreg(ctrl, offs);
  1906. tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
  1907. tmp &= ~ACC_CONTROL_RD_ERASED;
  1908. /* We need to turn on Read from erased paged protected by ECC */
  1909. if (ctrl->nand_version >= 0x0702)
  1910. tmp |= ACC_CONTROL_RD_ERASED;
  1911. tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
  1912. if (ctrl->features & BRCMNAND_HAS_PREFETCH)
  1913. tmp &= ~ACC_CONTROL_PREFETCH;
  1914. nand_writereg(ctrl, offs, tmp);
  1915. return 0;
  1916. }
  1917. #ifndef __UBOOT__
  1918. static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
  1919. #else
  1920. static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
  1921. #endif
  1922. {
  1923. struct brcmnand_controller *ctrl = host->ctrl;
  1924. #ifndef __UBOOT__
  1925. struct platform_device *pdev = host->pdev;
  1926. #else
  1927. struct udevice *pdev = host->pdev;
  1928. #endif /* __UBOOT__ */
  1929. struct mtd_info *mtd;
  1930. struct nand_chip *chip;
  1931. int ret;
  1932. u16 cfg_offs;
  1933. #ifndef __UBOOT__
  1934. ret = of_property_read_u32(dn, "reg", &host->cs);
  1935. #else
  1936. ret = ofnode_read_s32(dn, "reg", &host->cs);
  1937. #endif
  1938. if (ret) {
  1939. dev_err(&pdev->dev, "can't get chip-select\n");
  1940. return -ENXIO;
  1941. }
  1942. mtd = nand_to_mtd(&host->chip);
  1943. chip = &host->chip;
  1944. nand_set_flash_node(chip, dn);
  1945. nand_set_controller_data(chip, host);
  1946. #ifndef __UBOOT__
  1947. mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
  1948. host->cs);
  1949. #else
  1950. mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d",
  1951. host->cs);
  1952. #endif /* __UBOOT__ */
  1953. if (!mtd->name)
  1954. return -ENOMEM;
  1955. mtd->owner = THIS_MODULE;
  1956. #ifndef __UBOOT__
  1957. mtd->dev.parent = &pdev->dev;
  1958. #else
  1959. mtd->dev->parent = pdev;
  1960. #endif /* __UBOOT__ */
  1961. chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
  1962. chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
  1963. chip->cmd_ctrl = brcmnand_cmd_ctrl;
  1964. chip->cmdfunc = brcmnand_cmdfunc;
  1965. chip->waitfunc = brcmnand_waitfunc;
  1966. chip->read_byte = brcmnand_read_byte;
  1967. chip->read_buf = brcmnand_read_buf;
  1968. chip->write_buf = brcmnand_write_buf;
  1969. chip->ecc.mode = NAND_ECC_HW;
  1970. chip->ecc.read_page = brcmnand_read_page;
  1971. chip->ecc.write_page = brcmnand_write_page;
  1972. chip->ecc.read_page_raw = brcmnand_read_page_raw;
  1973. chip->ecc.write_page_raw = brcmnand_write_page_raw;
  1974. chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
  1975. chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
  1976. chip->ecc.read_oob = brcmnand_read_oob;
  1977. chip->ecc.write_oob = brcmnand_write_oob;
  1978. chip->controller = &ctrl->controller;
  1979. /*
  1980. * The bootloader might have configured 16bit mode but
  1981. * NAND READID command only works in 8bit mode. We force
  1982. * 8bit mode here to ensure that NAND READID commands works.
  1983. */
  1984. cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
  1985. nand_writereg(ctrl, cfg_offs,
  1986. nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
  1987. ret = nand_scan_ident(mtd, 1, NULL);
  1988. if (ret)
  1989. return ret;
  1990. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1991. /*
  1992. * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
  1993. * to/from, and have nand_base pass us a bounce buffer instead, as
  1994. * needed.
  1995. */
  1996. chip->options |= NAND_USE_BOUNCE_BUFFER;
  1997. if (chip->bbt_options & NAND_BBT_USE_FLASH)
  1998. chip->bbt_options |= NAND_BBT_NO_OOB;
  1999. if (brcmnand_setup_dev(host))
  2000. return -ENXIO;
  2001. chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
  2002. /* only use our internal HW threshold */
  2003. mtd->bitflip_threshold = 1;
  2004. chip->ecc.layout = brcmstb_choose_ecc_layout(host);
  2005. if (!chip->ecc.layout)
  2006. return -ENXIO;
  2007. ret = nand_scan_tail(mtd);
  2008. if (ret)
  2009. return ret;
  2010. #ifndef __UBOOT__
  2011. ret = mtd_device_register(mtd, NULL, 0);
  2012. if (ret)
  2013. nand_cleanup(chip);
  2014. #else
  2015. ret = nand_register(0, mtd);
  2016. #endif /* __UBOOT__ */
  2017. return ret;
  2018. }
  2019. #ifndef __UBOOT__
  2020. static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
  2021. int restore)
  2022. {
  2023. struct brcmnand_controller *ctrl = host->ctrl;
  2024. u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
  2025. u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
  2026. BRCMNAND_CS_CFG_EXT);
  2027. u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
  2028. BRCMNAND_CS_ACC_CONTROL);
  2029. u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
  2030. u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
  2031. if (restore) {
  2032. nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
  2033. if (cfg_offs != cfg_ext_offs)
  2034. nand_writereg(ctrl, cfg_ext_offs,
  2035. host->hwcfg.config_ext);
  2036. nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
  2037. nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
  2038. nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
  2039. } else {
  2040. host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
  2041. if (cfg_offs != cfg_ext_offs)
  2042. host->hwcfg.config_ext =
  2043. nand_readreg(ctrl, cfg_ext_offs);
  2044. host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
  2045. host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
  2046. host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
  2047. }
  2048. }
  2049. static int brcmnand_suspend(struct device *dev)
  2050. {
  2051. struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
  2052. struct brcmnand_host *host;
  2053. list_for_each_entry(host, &ctrl->host_list, node)
  2054. brcmnand_save_restore_cs_config(host, 0);
  2055. ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
  2056. ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
  2057. ctrl->corr_stat_threshold =
  2058. brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
  2059. if (has_flash_dma(ctrl))
  2060. ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
  2061. return 0;
  2062. }
  2063. static int brcmnand_resume(struct device *dev)
  2064. {
  2065. struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
  2066. struct brcmnand_host *host;
  2067. if (has_flash_dma(ctrl)) {
  2068. flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
  2069. flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
  2070. }
  2071. brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
  2072. brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
  2073. brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
  2074. ctrl->corr_stat_threshold);
  2075. if (ctrl->soc) {
  2076. /* Clear/re-enable interrupt */
  2077. ctrl->soc->ctlrdy_ack(ctrl->soc);
  2078. ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
  2079. }
  2080. list_for_each_entry(host, &ctrl->host_list, node) {
  2081. struct nand_chip *chip = &host->chip;
  2082. brcmnand_save_restore_cs_config(host, 1);
  2083. /* Reset the chip, required by some chips after power-up */
  2084. nand_reset_op(chip);
  2085. }
  2086. return 0;
  2087. }
  2088. const struct dev_pm_ops brcmnand_pm_ops = {
  2089. .suspend = brcmnand_suspend,
  2090. .resume = brcmnand_resume,
  2091. };
  2092. EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
  2093. static const struct of_device_id brcmnand_of_match[] = {
  2094. { .compatible = "brcm,brcmnand-v4.0" },
  2095. { .compatible = "brcm,brcmnand-v5.0" },
  2096. { .compatible = "brcm,brcmnand-v6.0" },
  2097. { .compatible = "brcm,brcmnand-v6.1" },
  2098. { .compatible = "brcm,brcmnand-v6.2" },
  2099. { .compatible = "brcm,brcmnand-v7.0" },
  2100. { .compatible = "brcm,brcmnand-v7.1" },
  2101. { .compatible = "brcm,brcmnand-v7.2" },
  2102. {},
  2103. };
  2104. MODULE_DEVICE_TABLE(of, brcmnand_of_match);
  2105. #endif /* __UBOOT__ */
  2106. /***********************************************************************
  2107. * Platform driver setup (per controller)
  2108. ***********************************************************************/
  2109. #ifndef __UBOOT__
  2110. int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
  2111. #else
  2112. int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
  2113. #endif /* __UBOOT__ */
  2114. {
  2115. #ifndef __UBOOT__
  2116. struct device *dev = &pdev->dev;
  2117. struct device_node *dn = dev->of_node, *child;
  2118. #else
  2119. ofnode child;
  2120. struct udevice *pdev = dev;
  2121. #endif /* __UBOOT__ */
  2122. struct brcmnand_controller *ctrl;
  2123. #ifndef __UBOOT__
  2124. struct resource *res;
  2125. #else
  2126. struct resource res;
  2127. #endif /* __UBOOT__ */
  2128. int ret;
  2129. #ifndef __UBOOT__
  2130. /* We only support device-tree instantiation */
  2131. if (!dn)
  2132. return -ENODEV;
  2133. if (!of_match_node(brcmnand_of_match, dn))
  2134. return -ENODEV;
  2135. #endif /* __UBOOT__ */
  2136. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  2137. if (!ctrl)
  2138. return -ENOMEM;
  2139. #ifndef __UBOOT__
  2140. dev_set_drvdata(dev, ctrl);
  2141. #else
  2142. /*
  2143. * in u-boot, the data for the driver is allocated before probing
  2144. * so to keep the reference to ctrl, we store it in the variable soc
  2145. */
  2146. soc->ctrl = ctrl;
  2147. #endif /* __UBOOT__ */
  2148. ctrl->dev = dev;
  2149. init_completion(&ctrl->done);
  2150. init_completion(&ctrl->dma_done);
  2151. nand_hw_control_init(&ctrl->controller);
  2152. INIT_LIST_HEAD(&ctrl->host_list);
  2153. /* Is parameter page in big endian ? */
  2154. ctrl->parameter_page_big_endian =
  2155. dev_read_u32_default(dev, "parameter-page-big-endian", 1);
  2156. /* NAND register range */
  2157. #ifndef __UBOOT__
  2158. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2159. ctrl->nand_base = devm_ioremap_resource(dev, res);
  2160. #else
  2161. dev_read_resource(pdev, 0, &res);
  2162. ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res));
  2163. #endif
  2164. if (IS_ERR(ctrl->nand_base))
  2165. return PTR_ERR(ctrl->nand_base);
  2166. /* Enable clock before using NAND registers */
  2167. ctrl->clk = devm_clk_get(dev, "nand");
  2168. if (!IS_ERR(ctrl->clk)) {
  2169. ret = clk_prepare_enable(ctrl->clk);
  2170. if (ret)
  2171. return ret;
  2172. } else {
  2173. ret = PTR_ERR(ctrl->clk);
  2174. if (ret == -EPROBE_DEFER)
  2175. return ret;
  2176. ctrl->clk = NULL;
  2177. }
  2178. /* Initialize NAND revision */
  2179. ret = brcmnand_revision_init(ctrl);
  2180. if (ret)
  2181. goto err;
  2182. /*
  2183. * Most chips have this cache at a fixed offset within 'nand' block.
  2184. * Some must specify this region separately.
  2185. */
  2186. #ifndef __UBOOT__
  2187. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
  2188. if (res) {
  2189. ctrl->nand_fc = devm_ioremap_resource(dev, res);
  2190. if (IS_ERR(ctrl->nand_fc)) {
  2191. ret = PTR_ERR(ctrl->nand_fc);
  2192. goto err;
  2193. }
  2194. } else {
  2195. ctrl->nand_fc = ctrl->nand_base +
  2196. ctrl->reg_offsets[BRCMNAND_FC_BASE];
  2197. }
  2198. #else
  2199. if (!dev_read_resource_byname(pdev, "nand-cache", &res)) {
  2200. ctrl->nand_fc = devm_ioremap(dev, res.start,
  2201. resource_size(&res));
  2202. if (IS_ERR(ctrl->nand_fc)) {
  2203. ret = PTR_ERR(ctrl->nand_fc);
  2204. goto err;
  2205. }
  2206. } else {
  2207. ctrl->nand_fc = ctrl->nand_base +
  2208. ctrl->reg_offsets[BRCMNAND_FC_BASE];
  2209. }
  2210. #endif
  2211. #ifndef __UBOOT__
  2212. /* FLASH_DMA */
  2213. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
  2214. if (res) {
  2215. ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
  2216. if (IS_ERR(ctrl->flash_dma_base)) {
  2217. ret = PTR_ERR(ctrl->flash_dma_base);
  2218. goto err;
  2219. }
  2220. flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
  2221. flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
  2222. /* Allocate descriptor(s) */
  2223. ctrl->dma_desc = dmam_alloc_coherent(dev,
  2224. sizeof(*ctrl->dma_desc),
  2225. &ctrl->dma_pa, GFP_KERNEL);
  2226. if (!ctrl->dma_desc) {
  2227. ret = -ENOMEM;
  2228. goto err;
  2229. }
  2230. ctrl->dma_irq = platform_get_irq(pdev, 1);
  2231. if ((int)ctrl->dma_irq < 0) {
  2232. dev_err(dev, "missing FLASH_DMA IRQ\n");
  2233. ret = -ENODEV;
  2234. goto err;
  2235. }
  2236. ret = devm_request_irq(dev, ctrl->dma_irq,
  2237. brcmnand_dma_irq, 0, DRV_NAME,
  2238. ctrl);
  2239. if (ret < 0) {
  2240. dev_err(dev, "can't allocate IRQ %d: error %d\n",
  2241. ctrl->dma_irq, ret);
  2242. goto err;
  2243. }
  2244. dev_info(dev, "enabling FLASH_DMA\n");
  2245. }
  2246. #endif /* __UBOOT__ */
  2247. /* Disable automatic device ID config, direct addressing */
  2248. brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
  2249. CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
  2250. /* Disable XOR addressing */
  2251. brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
  2252. /* Read the write-protect configuration in the device tree */
  2253. wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
  2254. if (ctrl->features & BRCMNAND_HAS_WP) {
  2255. /* Permanently disable write protection */
  2256. if (wp_on == 2)
  2257. brcmnand_set_wp(ctrl, false);
  2258. } else {
  2259. wp_on = 0;
  2260. }
  2261. #ifndef __UBOOT__
  2262. /* IRQ */
  2263. ctrl->irq = platform_get_irq(pdev, 0);
  2264. if ((int)ctrl->irq < 0) {
  2265. dev_err(dev, "no IRQ defined\n");
  2266. ret = -ENODEV;
  2267. goto err;
  2268. }
  2269. /*
  2270. * Some SoCs integrate this controller (e.g., its interrupt bits) in
  2271. * interesting ways
  2272. */
  2273. if (soc) {
  2274. ctrl->soc = soc;
  2275. ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
  2276. DRV_NAME, ctrl);
  2277. /* Enable interrupt */
  2278. ctrl->soc->ctlrdy_ack(ctrl->soc);
  2279. ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
  2280. } else {
  2281. /* Use standard interrupt infrastructure */
  2282. ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
  2283. DRV_NAME, ctrl);
  2284. }
  2285. if (ret < 0) {
  2286. dev_err(dev, "can't allocate IRQ %d: error %d\n",
  2287. ctrl->irq, ret);
  2288. goto err;
  2289. }
  2290. #endif /* __UBOOT__ */
  2291. #ifndef __UBOOT__
  2292. for_each_available_child_of_node(dn, child) {
  2293. if (of_device_is_compatible(child, "brcm,nandcs")) {
  2294. struct brcmnand_host *host;
  2295. host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
  2296. if (!host) {
  2297. of_node_put(child);
  2298. ret = -ENOMEM;
  2299. goto err;
  2300. }
  2301. host->pdev = pdev;
  2302. host->ctrl = ctrl;
  2303. ret = brcmnand_init_cs(host, child);
  2304. if (ret) {
  2305. devm_kfree(dev, host);
  2306. continue; /* Try all chip-selects */
  2307. }
  2308. list_add_tail(&host->node, &ctrl->host_list);
  2309. }
  2310. }
  2311. #else
  2312. ofnode_for_each_subnode(child, dev_ofnode(dev)) {
  2313. if (ofnode_device_is_compatible(child, "brcm,nandcs")) {
  2314. struct brcmnand_host *host;
  2315. host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
  2316. if (!host) {
  2317. ret = -ENOMEM;
  2318. goto err;
  2319. }
  2320. host->pdev = pdev;
  2321. host->ctrl = ctrl;
  2322. ret = brcmnand_init_cs(host, child);
  2323. if (ret) {
  2324. devm_kfree(dev, host);
  2325. continue; /* Try all chip-selects */
  2326. }
  2327. list_add_tail(&host->node, &ctrl->host_list);
  2328. }
  2329. }
  2330. #endif /* __UBOOT__ */
  2331. /* No chip-selects could initialize properly */
  2332. if (list_empty(&ctrl->host_list)) {
  2333. ret = -ENODEV;
  2334. goto err;
  2335. }
  2336. return 0;
  2337. err:
  2338. #ifndef __UBOOT__
  2339. clk_disable_unprepare(ctrl->clk);
  2340. #else
  2341. if (ctrl->clk)
  2342. clk_disable(ctrl->clk);
  2343. #endif /* __UBOOT__ */
  2344. return ret;
  2345. }
  2346. EXPORT_SYMBOL_GPL(brcmnand_probe);
  2347. #ifndef __UBOOT__
  2348. int brcmnand_remove(struct platform_device *pdev)
  2349. {
  2350. struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
  2351. struct brcmnand_host *host;
  2352. list_for_each_entry(host, &ctrl->host_list, node)
  2353. nand_release(nand_to_mtd(&host->chip));
  2354. clk_disable_unprepare(ctrl->clk);
  2355. dev_set_drvdata(&pdev->dev, NULL);
  2356. return 0;
  2357. }
  2358. #else
  2359. int brcmnand_remove(struct udevice *pdev)
  2360. {
  2361. return 0;
  2362. }
  2363. #endif /* __UBOOT__ */
  2364. EXPORT_SYMBOL_GPL(brcmnand_remove);
  2365. MODULE_LICENSE("GPL v2");
  2366. MODULE_AUTHOR("Kevin Cernekee");
  2367. MODULE_AUTHOR("Brian Norris");
  2368. MODULE_DESCRIPTION("NAND driver for Broadcom chips");
  2369. MODULE_ALIAS("platform:brcmnand");