mt7628.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #ifndef _MT7628_H_
  8. #define _MT7628_H_
  9. #define SYSCTL_BASE 0x10000000
  10. #define SYSCTL_SIZE 0x100
  11. #define MEMCTL_BASE 0x10000300
  12. #define MEMCTL_SIZE 0x100
  13. #define RBUSCTL_BASE 0x10000400
  14. #define RBUSCTL_SIZE 0x100
  15. #define RGCTL_BASE 0x10001000
  16. #define RGCTL_SIZE 0x800
  17. #define SYSCTL_EFUSE_CFG_REG 0x08
  18. #define EFUSE_MT7688 0x100000
  19. #define SYSCTL_CHIP_REV_ID_REG 0x0c
  20. #define PKG_ID 0x10000
  21. #define PKG_ID_AN 1
  22. #define PKG_ID_KN 0
  23. #define VER_S 8
  24. #define VER_M 0xf00
  25. #define ECO_S 0
  26. #define ECO_M 0x0f
  27. #define SYSCTL_SYSCFG0_REG 0x10
  28. #define XTAL_FREQ_SEL 0x40
  29. #define XTAL_40MHZ 1
  30. #define XTAL_25MHZ 0
  31. #define CHIP_MODE_S 1
  32. #define CHIP_MODE_M 0x0e
  33. #define DRAM_TYPE 0x01
  34. #define DRAM_DDR1 1
  35. #define DRAM_DDR2 0
  36. #define SYSCTL_ROM_STATUS_REG 0x28
  37. #define SYSCTL_CLKCFG0_REG 0x2c
  38. #define DIS_BBP_SLEEP 0x08
  39. #define EN_BBP_CLK 0x04
  40. #define CPU_PLL_FROM_BBP 0x02
  41. #define CPU_PLL_FROM_XTAL 0x01
  42. #define SYSCTL_RSTCTL_REG 0x34
  43. #define MC_RST 0x400
  44. #define SYSCTL_AGPIO_CFG_REG 0x3c
  45. #define EPHY_GPIO_AIO_EN_S 17
  46. #define EPHY_GPIO_AIO_EN_M 0x1e0000
  47. #define SYSCTL_GPIO_MODE1_REG 0x60
  48. #define UART2_MODE_S 26
  49. #define UART2_MODE_M 0xc000000
  50. #define UART1_MODE_S 24
  51. #define UART1_MODE_M 0x3000000
  52. #define UART0_MODE_S 8
  53. #define UART0_MODE_M 0x300
  54. #define SPIS_MODE_S 2
  55. #define SPIS_MODE_M 0x0c
  56. #define RBUSCTL_DYN_CFG0_REG 0x40
  57. #define CPU_FDIV_S 8
  58. #define CPU_FDIV_M 0xf00
  59. #define CPU_FFRAC_S 0
  60. #define CPU_FFRAC_M 0x0f
  61. #define RGCTL_PMU_G0_REG 0x100
  62. #define PMU_CFG_EN 0x80000000
  63. #define RGCTL_PMU_G1_REG 0x104
  64. #define RG_BUCK_FPWM 0x02
  65. #define RGCTL_PMU_G3_REG 0x10c
  66. #define NI_DDRLDO_STB 0x40000
  67. #define NI_DDRLDO_EN 0x10000
  68. #define RG_DDRLDO_VOSEL 0x40
  69. #define RGCTL_DDR_PAD_CK_G0_REG 0x700
  70. #define RGCTL_DDR_PAD_CMD_G0_REG 0x708
  71. #define RGCTL_DDR_PAD_DQ_G0_REG 0x710
  72. #define RGCTL_DDR_PAD_DQS_G0_REG 0x718
  73. #define RTT_S 8
  74. #define RTT_M 0x700
  75. #define RGCTL_DDR_PAD_CK_G1_REG 0x704
  76. #define RGCTL_DDR_PAD_CMD_G1_REG 0x70c
  77. #define RGCTL_DDR_PAD_DQ_G1_REG 0x714
  78. #define RGCTL_DDR_PAD_DQS_G1_REG 0x71c
  79. #define DRVP_S 0
  80. #define DRVP_M 0x0f
  81. #define DRVN_S 8
  82. #define DRVN_M 0xf00
  83. #ifndef __ASSEMBLY__
  84. void mt7628_ddr_init(void);
  85. #endif
  86. #endif /* _MT7628_H_ */