lowlevel_init.S 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <config.h>
  8. #include <asm-offsets.h>
  9. #include <asm/cacheops.h>
  10. #include <asm/regdef.h>
  11. #include <asm/mipsregs.h>
  12. #include <asm/addrspace.h>
  13. #include <asm/asm.h>
  14. #include "mt7628.h"
  15. /* Set temporary stack address range */
  16. #ifndef CONFIG_SYS_INIT_SP_ADDR
  17. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
  18. CONFIG_SYS_INIT_SP_OFFSET)
  19. #endif
  20. #define CACHE_STACK_SIZE 0x4000
  21. #define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
  22. #define DELAY_USEC(us) ((58 * (us)) / 3)
  23. .set noreorder
  24. LEAF(mips_sram_init)
  25. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  26. /* Setup CPU PLL */
  27. li t0, DELAY_USEC(1000000)
  28. li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
  29. li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)
  30. _check_rom_status:
  31. lw t3, 0(t1)
  32. andi t3, t3, 1
  33. bnez t3, _rom_normal
  34. subu t0, t0, 1
  35. bnez t0, _check_rom_status
  36. nop
  37. lw t3, 0(t2)
  38. ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
  39. xori t3, CPU_PLL_FROM_BBP
  40. b _cpu_pll_done
  41. nop
  42. _rom_normal:
  43. lw t3, 0(t2)
  44. ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL | \
  45. DIS_BBP_SLEEP | EN_BBP_CLK)
  46. xori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
  47. _cpu_pll_done:
  48. sw t3, 0(t2)
  49. li t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG)
  50. lw t3, 0(t2)
  51. ori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
  52. xori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
  53. ori t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S))
  54. sw t3, 0(t2)
  55. /* Clear WST & SPR bits in ErrCtl */
  56. mfc0 t0, CP0_ECC
  57. ins t0, zero, 30, 2
  58. mtc0 t0, CP0_ECC
  59. ehb
  60. /* Simply initialize I-Cache */
  61. li a0, 0
  62. li a1, CONFIG_SYS_ICACHE_SIZE
  63. mtc0 zero, CP0_TAGLO /* Zero to DDataLo */
  64. 1: cache INDEX_STORE_TAG_I, 0(a0)
  65. addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE
  66. bne a0, a1, 1b
  67. nop
  68. /* Simply initialize D-Cache */
  69. li a0, 0
  70. li a1, CONFIG_SYS_DCACHE_SIZE
  71. mtc0 zero, CP0_TAGLO, 2
  72. 2: cache INDEX_STORE_TAG_D, 0(a0)
  73. addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
  74. bne a0, a1, 2b
  75. nop
  76. /* Set KSEG0 Cachable */
  77. mfc0 t0, CP0_CONFIG
  78. and t0, t0, MIPS_CONF_IMPL
  79. or t0, t0, CONF_CM_CACHABLE_NONCOHERENT
  80. mtc0 t0, CP0_CONFIG
  81. ehb
  82. /* Lock D-Cache */
  83. PTR_LI a0, CACHE_STACK_BASE /* D-Cache lock base */
  84. li a1, CACHE_STACK_SIZE /* D-Cache lock size */
  85. li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */
  86. 3:
  87. /* Lock one cacheline */
  88. and t0, a0, a2
  89. ori t0, 0xe0 /* Valid & Dirty & Lock bits */
  90. mtc0 t0, CP0_TAGLO, 2 /* Write to DTagLo */
  91. ehb
  92. cache INDEX_STORE_TAG_D, 0(a0)
  93. addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
  94. sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
  95. bnez a1, 3b
  96. nop
  97. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  98. jr ra
  99. nop
  100. END(mips_sram_init)
  101. NESTED(lowlevel_init, 0, ra)
  102. /* Save ra and do real lowlevel initialization */
  103. move s0, ra
  104. PTR_LA t9, mt7628_init
  105. jalr t9
  106. nop
  107. move ra, s0
  108. #if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
  109. /* Set malloc base */
  110. li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
  111. PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
  112. #endif
  113. /* Write back data in locked cache to DRAM */
  114. PTR_LI a0, CACHE_STACK_BASE /* D-Cache unlock base */
  115. li a1, CACHE_STACK_SIZE /* D-Cache unlock size */
  116. 1:
  117. cache HIT_WRITEBACK_INV_D, 0(a0)
  118. addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
  119. sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
  120. bnez a1, 1b
  121. nop
  122. /* Set KSEG0 Uncached */
  123. mfc0 t0, CP0_CONFIG
  124. and t0, t0, MIPS_CONF_IMPL
  125. or t0, t0, CONF_CM_UNCACHED
  126. mtc0 t0, CP0_CONFIG
  127. ehb
  128. jr ra
  129. nop
  130. END(lowlevel_init)