init.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <dm/uclass.h>
  11. #include <dt-bindings/clock/mt7628-clk.h>
  12. #include <linux/io.h>
  13. #include "mt7628.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. static void set_init_timer_freq(void)
  16. {
  17. void __iomem *sysc;
  18. u32 bs, val, timer_freq_post;
  19. sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
  20. /* We can't use the clk driver as the DM has not been initialized yet */
  21. bs = readl(sysc + SYSCTL_SYSCFG0_REG);
  22. if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) {
  23. gd->arch.timer_freq = 25000000;
  24. timer_freq_post = 575000000;
  25. } else {
  26. gd->arch.timer_freq = 40000000;
  27. timer_freq_post = 580000000;
  28. }
  29. val = readl(sysc + SYSCTL_CLKCFG0_REG);
  30. if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)))
  31. gd->arch.timer_freq = timer_freq_post;
  32. }
  33. void mt7628_init(void)
  34. {
  35. set_init_timer_freq();
  36. mt7628_ddr_init();
  37. }
  38. int print_cpuinfo(void)
  39. {
  40. void __iomem *sysc;
  41. struct udevice *clkdev;
  42. u32 val, ver, eco, pkg, ddr, chipmode, ee;
  43. ulong cpu_clk, bus_clk, xtal_clk, timer_freq;
  44. struct clk clk;
  45. int ret;
  46. sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
  47. val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
  48. ver = (val & VER_M) >> VER_S;
  49. eco = (val & ECO_M) >> ECO_S;
  50. pkg = !!(val & PKG_ID);
  51. val = readl(sysc + SYSCTL_SYSCFG0_REG);
  52. ddr = val & DRAM_TYPE;
  53. chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
  54. val = readl(sysc + SYSCTL_EFUSE_CFG_REG);
  55. ee = val & EFUSE_MT7688;
  56. printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n",
  57. ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco);
  58. printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n",
  59. ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
  60. chipmode & 0x02 ? "XTAL" : "CPLL");
  61. ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk),
  62. &clkdev);
  63. if (ret)
  64. return ret;
  65. clk.dev = clkdev;
  66. clk.id = CLK_CPU;
  67. cpu_clk = clk_get_rate(&clk);
  68. clk.id = CLK_SYS;
  69. bus_clk = clk_get_rate(&clk);
  70. clk.id = CLK_XTAL;
  71. xtal_clk = clk_get_rate(&clk);
  72. clk.id = CLK_MIPS_CNT;
  73. timer_freq = clk_get_rate(&clk);
  74. /* Set final timer frequency */
  75. if (timer_freq)
  76. gd->arch.timer_freq = timer_freq;
  77. printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n",
  78. cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
  79. return 0;
  80. }
  81. ulong notrace get_tbclk(void)
  82. {
  83. return gd->arch.timer_freq;
  84. }