ddr.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <asm/addrspace.h>
  9. #include <linux/bitops.h>
  10. #include <linux/sizes.h>
  11. #include <linux/io.h>
  12. #include <mach/ddr.h>
  13. #include <mach/mc.h>
  14. #include "mt7628.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* DDR2 DQ_DLY */
  17. #define DDR2_DQ_DLY \
  18. ((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \
  19. (0x2 << DQ1_DELAY_FINE_TUNING_S) | \
  20. (0x8 << DQ0_DELAY_COARSE_TUNING_S) | \
  21. (0x2 << DQ0_DELAY_FINE_TUNING_S))
  22. /* DDR2 DQS_DLY */
  23. #define DDR2_DQS_DLY \
  24. ((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \
  25. (0x3 << DQS1_DELAY_FINE_TUNING_S) | \
  26. (0x8 << DQS0_DELAY_COARSE_TUNING_S) | \
  27. (0x3 << DQS0_DELAY_FINE_TUNING_S))
  28. const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = {
  29. [DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 },
  30. [DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 },
  31. [DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 },
  32. [DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 },
  33. [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 },
  34. };
  35. const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = {
  36. [DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 },
  37. [DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 },
  38. [DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 },
  39. [DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 },
  40. [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 },
  41. };
  42. const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = {
  43. [DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A },
  44. [DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A },
  45. [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A },
  46. [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A },
  47. };
  48. const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = {
  49. [DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 },
  50. [DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 },
  51. [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 },
  52. [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 },
  53. };
  54. static void mt7628_memc_reset(int assert)
  55. {
  56. void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
  57. if (assert)
  58. setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
  59. else
  60. clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
  61. }
  62. static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type)
  63. {
  64. void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE);
  65. u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1;
  66. setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN);
  67. if (ddr_type == DRAM_DDR1)
  68. setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
  69. else
  70. clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
  71. setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN);
  72. __udelay(250 * 50);
  73. setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB);
  74. setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM);
  75. ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG);
  76. cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG);
  77. dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG);
  78. dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG);
  79. dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG);
  80. dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG);
  81. ck_pad1 &= ~(DRVP_M | DRVN_M);
  82. cmd_pad1 &= ~(DRVP_M | DRVN_M);
  83. dq_pad0 &= ~RTT_M;
  84. dq_pad1 &= ~(DRVP_M | DRVN_M);
  85. dqs_pad0 &= ~RTT_M;
  86. dqs_pad1 &= ~(DRVP_M | DRVN_M);
  87. if (pkg_type == PKG_ID_KN) {
  88. ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
  89. cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
  90. dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
  91. dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
  92. } else {
  93. ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
  94. cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S);
  95. dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
  96. if (ddr_type == DRAM_DDR1)
  97. dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S);
  98. else
  99. dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S);
  100. }
  101. writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG);
  102. writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG);
  103. writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG);
  104. writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG);
  105. writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG);
  106. writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG);
  107. }
  108. void mt7628_ddr_init(void)
  109. {
  110. void __iomem *sysc;
  111. int ddr_type, pkg_type, lspd;
  112. struct mc_ddr_init_param param;
  113. sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
  114. ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE;
  115. pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID);
  116. lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
  117. (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
  118. mt7628_memc_reset(1);
  119. __udelay(200);
  120. mt7628_ddr_pad_ldo_config(ddr_type, pkg_type);
  121. param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
  122. param.dq_dly = DDR2_DQ_DLY;
  123. param.dqs_dly = DDR2_DQS_DLY;
  124. param.mc_reset = mt7628_memc_reset;
  125. param.memsize = 0;
  126. param.bus_width = 0;
  127. if (pkg_type == PKG_ID_KN)
  128. ddr_type = DRAM_DDR1;
  129. if (ddr_type == DRAM_DDR1) {
  130. if (lspd)
  131. param.cfgs = ddr1_cfgs_160mhz;
  132. else
  133. param.cfgs = ddr1_cfgs_200mhz;
  134. ddr1_init(&param);
  135. } else {
  136. if (lspd)
  137. param.cfgs = ddr2_cfgs_160mhz;
  138. else
  139. param.cfgs = ddr2_cfgs_200mhz;
  140. ddr2_init(&param);
  141. }
  142. ddr_calibrate(param.memc, param.memsize, param.bus_width);
  143. gd->ram_size = param.memsize;
  144. }