mc.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #ifndef _MTMIPS_MC_H_
  8. #define _MTMIPS_MC_H_
  9. #define MEMCTL_SDRAM_CFG0_REG 0x00
  10. #define DIS_CLK_GT 0x80000000
  11. #define CLK_SLEW_S 29
  12. #define CLK_SLEW_M 0x60000000
  13. #define TWR 0x10000000
  14. #define TMRD_S 24
  15. #define TMRD_M 0xf000000
  16. #define TRFC_S 20
  17. #define TRFC_M 0xf00000
  18. #define TCAS_S 16
  19. #define TCAS_M 0x30000
  20. #define TRAS_S 12
  21. #define TRAS_M 0xf000
  22. #define TRCD_S 8
  23. #define TRCD_M 0x300
  24. #define TRC_S 4
  25. #define TRC_M 0xf0
  26. #define TRP_S 0
  27. #define TRP_M 0x03
  28. #define MEMCTL_SDRAM_CFG1_REG 0x04
  29. #define SDRAM_INIT_START 0x80000000
  30. #define SDRAM_INIT_DONE 0x40000000
  31. #define RBC_MAPPING 0x20000000
  32. #define PWR_DOWN_EN 0x10000000
  33. #define PWR_DOWN_MODE 0x8000000
  34. #define SDRAM_WIDTH 0x1000000
  35. #define NUMCOLS_S 20
  36. #define NUMCOLS_M 0x300000
  37. #define NUMROWS_S 16
  38. #define NUMROWS_M 0x30000
  39. #define TREFR_S 0
  40. #define TREFR_M 0xffff
  41. #define MEMCTL_DDR_SELF_REFRESH_REG 0x10
  42. #define ODT_SRC_SEL_S 24
  43. #define ODT_SRC_SEL_M 0xf000000
  44. #define ODT_OFF_DLY_S 20
  45. #define ODT_OFF_DLY_M 0xf00000
  46. #define ODT_ON_DLY_S 16
  47. #define ODT_ON_DLY_M 0xf0000
  48. #define SR_AUTO_EN 0x10
  49. #define SRACK_B 0x02
  50. #define SRREQ_B 0x01
  51. #define MEMCTL_PWR_SAVE_CNT_REG 0x14
  52. #define PD_CNT_S 24
  53. #define PD_CNT_M 0xff000000
  54. #define SR_TAR_CNT_S 0
  55. #define SR_TAR_CNT_M 0xffffff
  56. #define MEMCTL_DLL_DBG_REG 0x20
  57. #define TDC_STABLE_S 12
  58. #define TDC_STABLE_M 0x3f000
  59. #define MST_DLY_SEL_S 4
  60. #define MST_DLY_SEL_M 0xff0
  61. #define CURR_STATE_S 1
  62. #define CURR_STATE_M 0x06
  63. #define ADLL_LOCK_DONE 0x01
  64. #define MEMCTL_DDR_CFG0_REG 0x40
  65. #define T_RRD_S 28
  66. #define T_RRD_M 0xf0000000
  67. #define T_RAS_S 23
  68. #define T_RAS_M 0xf800000
  69. #define T_RP_S 19
  70. #define T_RP_M 0x780000
  71. #define T_RFC_S 13
  72. #define T_RFC_M 0x7e000
  73. #define T_REFI_S 0
  74. #define T_REFI_M 0x1fff
  75. #define MEMCTL_DDR_CFG1_REG 0x44
  76. #define T_WTR_S 28
  77. #define T_WTR_M 0xf0000000
  78. #define T_RTP_S 24
  79. #define T_RTP_M 0xf000000
  80. #define USER_DATA_WIDTH 0x200000
  81. #define IND_SDRAM_SIZE_S 18
  82. #define IND_SDRAM_SIZE_M 0x1c0000
  83. #define IND_SDRAM_SIZE_8MB 1
  84. #define IND_SDRAM_SIZE_16MB 2
  85. #define IND_SDRAM_SIZE_32MB 3
  86. #define IND_SDRAM_SIZE_64MB 4
  87. #define IND_SDRAM_SIZE_128MB 5
  88. #define IND_SDRAM_SIZE_256MB 6
  89. #define IND_SDRAM_WIDTH_S 16
  90. #define IND_SDRAM_WIDTH_M 0x30000
  91. #define IND_SDRAM_WIDTH_8BIT 1
  92. #define IND_SDRAM_WIDTH_16BIT 2
  93. #define EXT_BANK_S 14
  94. #define EXT_BANK_M 0xc000
  95. #define TOTAL_SDRAM_WIDTH_S 12
  96. #define TOTAL_SDRAM_WIDTH_M 0x3000
  97. #define T_WR_S 8
  98. #define T_WR_M 0xf00
  99. #define T_MRD_S 4
  100. #define T_MRD_M 0xf0
  101. #define T_RCD_S 0
  102. #define T_RCD_M 0x0f
  103. #define MEMCTL_DDR_CFG2_REG 0x48
  104. #define REGE 0x80000000
  105. #define DDR2_MODE 0x40000000
  106. #define DQS0_GATING_WINDOW_S 28
  107. #define DQS0_GATING_WINDOW_M 0x30000000
  108. #define DQS1_GATING_WINDOW_S 26
  109. #define DQS1_GATING_WINDOW_M 0xc000000
  110. #define PD 0x1000
  111. #define WR_S 9
  112. #define WR_M 0xe00
  113. #define DLLRESET 0x100
  114. #define TESTMODE 0x80
  115. #define CAS_LATENCY_S 4
  116. #define CAS_LATENCY_M 0x70
  117. #define BURST_TYPE 0x08
  118. #define BURST_LENGTH_S 0
  119. #define BURST_LENGTH_M 0x07
  120. #define MEMCTL_DDR_CFG3_REG 0x4c
  121. #define Q_OFF 0x1000
  122. #define RDOS 0x800
  123. #define DIS_DIFF_DQS 0x400
  124. #define OCD_S 7
  125. #define OCD_M 0x380
  126. #define RTT1 0x40
  127. #define ADDITIVE_LATENCY_S 3
  128. #define ADDITIVE_LATENCY_M 0x38
  129. #define RTT0 0x04
  130. #define DS 0x02
  131. #define DLL 0x01
  132. #define MEMCTL_DDR_CFG4_REG 0x50
  133. #define FAW_S 0
  134. #define FAW_M 0x0f
  135. #define MEMCTL_DDR_DQ_DLY_REG 0x60
  136. #define DQ1_DELAY_SEL_S 24
  137. #define DQ1_DELAY_SEL_M 0xff000000
  138. #define DQ0_DELAY_SEL_S 16
  139. #define DQ0_DELAY_SEL_M 0xff0000
  140. #define DQ1_DELAY_COARSE_TUNING_S 12
  141. #define DQ1_DELAY_COARSE_TUNING_M 0xf000
  142. #define DQ1_DELAY_FINE_TUNING_S 8
  143. #define DQ1_DELAY_FINE_TUNING_M 0xf00
  144. #define DQ0_DELAY_COARSE_TUNING_S 4
  145. #define DQ0_DELAY_COARSE_TUNING_M 0xf0
  146. #define DQ0_DELAY_FINE_TUNING_S 0
  147. #define DQ0_DELAY_FINE_TUNING_M 0x0f
  148. #define MEMCTL_DDR_DQS_DLY_REG 0x64
  149. #define DQS1_DELAY_SEL_S 24
  150. #define DQS1_DELAY_SEL_M 0xff000000
  151. #define DQS0_DELAY_SEL_S 16
  152. #define DQS0_DELAY_SEL_M 0xff0000
  153. #define DQS1_DELAY_COARSE_TUNING_S 12
  154. #define DQS1_DELAY_COARSE_TUNING_M 0xf000
  155. #define DQS1_DELAY_FINE_TUNING_S 8
  156. #define DQS1_DELAY_FINE_TUNING_M 0xf00
  157. #define DQS0_DELAY_COARSE_TUNING_S 4
  158. #define DQS0_DELAY_COARSE_TUNING_M 0xf0
  159. #define DQS0_DELAY_FINE_TUNING_S 0
  160. #define DQS0_DELAY_FINE_TUNING_M 0x0f
  161. #define MEMCTL_DDR_DLL_SLV_REG 0x68
  162. #define DLL_SLV_UPDATE_MODE 0x100
  163. #define DQS_DLY_SEL_EN 0x80
  164. #define DQ_DLY_SEL_EN 0x01
  165. #endif /* _MTMIPS_MC_H_ */