mt7628a.dtsi 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/clock/mt7628-clk.h>
  3. #include <dt-bindings/reset/mt7628-reset.h>
  4. / {
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. compatible = "ralink,mt7628a-soc";
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. cpu@0 {
  12. compatible = "mti,mips24KEc";
  13. device_type = "cpu";
  14. reg = <0>;
  15. };
  16. };
  17. cpuintc: interrupt-controller {
  18. #address-cells = <0>;
  19. #interrupt-cells = <1>;
  20. interrupt-controller;
  21. compatible = "mti,cpu-interrupt-controller";
  22. };
  23. clk48m: clk48m@0 {
  24. compatible = "fixed-clock";
  25. clock-frequency = <48000000>;
  26. #clock-cells = <0>;
  27. };
  28. palmbus: palmbus@10000000 {
  29. compatible = "palmbus", "simple-bus";
  30. reg = <0x10000000 0x200000>;
  31. ranges = <0x0 0x10000000 0x1FFFFF>;
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. sysc: system-controller@0 {
  35. compatible = "ralink,mt7620a-sysc", "syscon";
  36. reg = <0x0 0x100>;
  37. };
  38. reboot: resetctl-reboot {
  39. compatible = "resetctl-reboot";
  40. resets = <&rstctrl MT7628_SYS_RST>;
  41. reset-names = "sysreset";
  42. };
  43. clkctrl: clkctrl@0x2c {
  44. reg = <0x2c 0x8>, <0x10 0x4>;
  45. reg-names = "syscfg0", "clkcfg";
  46. compatible = "mediatek,mt7628-clk";
  47. #clock-cells = <1>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. rstctrl: rstctrl@0x34 {
  51. reg = <0x34 0x4>;
  52. compatible = "mediatek,mtmips-reset";
  53. #reset-cells = <1>;
  54. };
  55. pinctrl: pinctrl@60 {
  56. compatible = "mediatek,mt7628-pinctrl";
  57. reg = <0x3c 0x2c>, <0x1300 0x100>;
  58. reg-names = "gpiomode", "padconf";
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&state_default>;
  61. state_default: pin_state {
  62. };
  63. spi_single_pins: spi_single_pins {
  64. groups = "spi";
  65. function = "spi";
  66. };
  67. spi_dual_pins: spi_dual_pins {
  68. spi_master_pins {
  69. groups = "spi";
  70. function = "spi";
  71. };
  72. spi_cs1_pin {
  73. groups = "spi cs1";
  74. function = "spi cs1";
  75. };
  76. };
  77. uart0_pins: uart0_pins {
  78. groups = "uart0";
  79. function = "uart0";
  80. };
  81. uart1_pins: uart1_pins {
  82. groups = "uart1";
  83. function = "uart1";
  84. };
  85. uart2_pins: uart2_pins {
  86. groups = "uart2";
  87. function = "uart2";
  88. };
  89. uart2_pwm_pins: uart2_pwm_pins {
  90. groups = "spis";
  91. function = "pwm_uart2";
  92. };
  93. i2c_pins: i2c_pins {
  94. groups = "i2c";
  95. function = "i2c";
  96. };
  97. ephy_iot_mode: ephy_iot_mode {
  98. ephy4_1_dis {
  99. groups = "ephy4_1_pad";
  100. function = "digital";
  101. };
  102. ephy0_en {
  103. groups = "ephy0";
  104. function = "enable";
  105. };
  106. };
  107. ephy_router_mode: ephy_router_mode {
  108. ephy4_1_en {
  109. groups = "ephy4_1_pad";
  110. function = "analog";
  111. };
  112. ephy0_en {
  113. groups = "ephy0";
  114. function = "enable";
  115. };
  116. };
  117. sd_iot_mode: sd_iot_mode {
  118. ephy4_1_dis {
  119. groups = "ephy4_1_pad";
  120. function = "digital";
  121. };
  122. sdxc_en {
  123. groups = "sdmode";
  124. function = "sdxc";
  125. };
  126. sdxc_iot_mode {
  127. groups = "sd router";
  128. function = "iot";
  129. };
  130. sd_clk_pad {
  131. pins = "sd_clk";
  132. drive-strength-4g = <8>;
  133. };
  134. };
  135. sd_router_mode: sd_router_mode {
  136. sdxc_router_mode {
  137. groups = "sd router";
  138. function = "router";
  139. };
  140. sdxc_map_pins {
  141. groups = "gpio0", "i2s", "sdmode", \
  142. "i2c", "uart1";
  143. function = "gpio";
  144. };
  145. sd_clk_pad {
  146. pins = "gpio0";
  147. drive-strength-28 = <8>;
  148. };
  149. };
  150. emmc_iot_8bit_mode: emmc_iot_8bit_mode {
  151. ephy4_1_dis {
  152. groups = "ephy4_1_pad";
  153. function = "digital";
  154. };
  155. emmc_en {
  156. groups = "sdmode";
  157. function = "sdxc";
  158. };
  159. emmc_iot_mode {
  160. groups = "sd router";
  161. function = "iot";
  162. };
  163. emmc_d4_d5 {
  164. groups = "uart2";
  165. function = "sdxc d5 d4";
  166. };
  167. emmc_d6 {
  168. groups = "pwm1";
  169. function = "sdxc d6";
  170. };
  171. emmc_d7 {
  172. groups = "pwm0";
  173. function = "sdxc d7";
  174. };
  175. sd_clk_pad {
  176. pins = "sd_clk";
  177. drive-strength-4g = <8>;
  178. };
  179. };
  180. };
  181. watchdog: watchdog@100 {
  182. compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
  183. reg = <0x100 0x30>;
  184. resets = <&rstctrl MT7628_TIMER_RST>;
  185. reset-names = "wdt";
  186. interrupt-parent = <&intc>;
  187. interrupts = <24>;
  188. };
  189. intc: interrupt-controller@200 {
  190. compatible = "ralink,rt2880-intc";
  191. reg = <0x200 0x100>;
  192. interrupt-controller;
  193. #interrupt-cells = <1>;
  194. resets = <&rstctrl MT7628_INT_RST>;
  195. reset-names = "intc";
  196. interrupt-parent = <&cpuintc>;
  197. interrupts = <2>;
  198. ralink,intc-registers = <0x9c 0xa0
  199. 0x6c 0xa4
  200. 0x80 0x78>;
  201. };
  202. memory-controller@300 {
  203. compatible = "ralink,mt7620a-memc";
  204. reg = <0x300 0x100>;
  205. };
  206. gpio@600 {
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  210. reg = <0x600 0x100>;
  211. resets = <&rstctrl MT7628_PIO_RST>;
  212. reset-names = "pio";
  213. interrupt-parent = <&intc>;
  214. interrupts = <6>;
  215. gpio0: bank@0 {
  216. reg = <0>;
  217. compatible = "mtk,mt7621-gpio-bank";
  218. gpio-controller;
  219. #gpio-cells = <2>;
  220. };
  221. gpio1: bank@1 {
  222. reg = <1>;
  223. compatible = "mtk,mt7621-gpio-bank";
  224. gpio-controller;
  225. #gpio-cells = <2>;
  226. };
  227. gpio2: bank@2 {
  228. reg = <2>;
  229. compatible = "mtk,mt7621-gpio-bank";
  230. gpio-controller;
  231. #gpio-cells = <2>;
  232. };
  233. };
  234. spi0: spi@b00 {
  235. compatible = "ralink,mt7621-spi";
  236. reg = <0xb00 0x40>;
  237. resets = <&rstctrl MT7628_SPI_RST>;
  238. reset-names = "spi";
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. clocks = <&clkctrl CLK_SPI>;
  242. };
  243. uart0: uartlite@c00 {
  244. compatible = "mediatek,hsuart", "ns16550a";
  245. reg = <0xc00 0x100>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&uart0_pins>;
  248. clocks = <&clkctrl CLK_UART0>;
  249. resets = <&rstctrl MT7628_UART0_RST>;
  250. reset-names = "uart0";
  251. interrupt-parent = <&intc>;
  252. interrupts = <20>;
  253. reg-shift = <2>;
  254. };
  255. uart1: uart1@d00 {
  256. compatible = "mediatek,hsuart", "ns16550a";
  257. reg = <0xd00 0x100>;
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&uart1_pins>;
  260. clocks = <&clkctrl CLK_UART1>;
  261. resets = <&rstctrl MT7628_UART1_RST>;
  262. reset-names = "uart1";
  263. interrupt-parent = <&intc>;
  264. interrupts = <21>;
  265. reg-shift = <2>;
  266. };
  267. uart2: uart2@e00 {
  268. compatible = "mediatek,hsuart", "ns16550a";
  269. reg = <0xe00 0x100>;
  270. pinctrl-names = "default";
  271. pinctrl-0 = <&uart2_pins>;
  272. clocks = <&clkctrl CLK_UART2>;
  273. resets = <&rstctrl MT7628_UART2_RST>;
  274. reset-names = "uart2";
  275. interrupt-parent = <&intc>;
  276. interrupts = <22>;
  277. reg-shift = <2>;
  278. };
  279. };
  280. eth: eth@10110000 {
  281. compatible = "mediatek,mt7628-eth";
  282. reg = <0x10100000 0x10000
  283. 0x10110000 0x8000>;
  284. resets = <&rstctrl MT7628_EPHY_RST>;
  285. reset-names = "ephy";
  286. syscon = <&sysc>;
  287. };
  288. usb_phy: usb-phy@10120000 {
  289. compatible = "mediatek,mt7628-usbphy";
  290. reg = <0x10120000 0x1000>;
  291. #phy-cells = <0>;
  292. ralink,sysctl = <&sysc>;
  293. resets = <&rstctrl MT7628_UPHY_RST>;
  294. reset-names = "phy";
  295. clocks = <&clkctrl CLK_UPHY>;
  296. clock-names = "cg";
  297. };
  298. ehci@101c0000 {
  299. compatible = "generic-ehci";
  300. reg = <0x101c0000 0x1000>;
  301. phys = <&usb_phy>;
  302. phy-names = "usb";
  303. interrupt-parent = <&intc>;
  304. interrupts = <18>;
  305. };
  306. mmc: mmc@10130000 {
  307. compatible = "mediatek,mt7620-mmc";
  308. reg = <0x10130000 0x4000>;
  309. builtin-cd = <1>;
  310. r_smpl = <1>;
  311. clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
  312. clock-names = "source", "hclk";
  313. resets = <&rstctrl MT7628_SDXC_RST>;
  314. status = "disabled";
  315. };
  316. };