Kconfig 13 KB

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  1. menu "MIPS architecture"
  2. depends on MIPS
  3. config SYS_ARCH
  4. default "mips"
  5. config SYS_CPU
  6. default "mips32" if CPU_MIPS32
  7. default "mips64" if CPU_MIPS64
  8. choice
  9. prompt "Target select"
  10. optional
  11. config TARGET_QEMU_MIPS
  12. bool "Support qemu-mips"
  13. select ROM_EXCEPTION_VECTORS
  14. select SUPPORTS_BIG_ENDIAN
  15. select SUPPORTS_CPU_MIPS32_R1
  16. select SUPPORTS_CPU_MIPS32_R2
  17. select SUPPORTS_CPU_MIPS64_R1
  18. select SUPPORTS_CPU_MIPS64_R2
  19. select SUPPORTS_LITTLE_ENDIAN
  20. config TARGET_MALTA
  21. bool "Support malta"
  22. select DM
  23. select DM_SERIAL
  24. select DYNAMIC_IO_PORT_BASE
  25. select MIPS_CM
  26. select MIPS_INSERT_BOOT_CONFIG
  27. select MIPS_L1_CACHE_SHIFT_6
  28. select MIPS_L2_CACHE
  29. select OF_CONTROL
  30. select OF_ISA_BUS
  31. select ROM_EXCEPTION_VECTORS
  32. select SUPPORTS_BIG_ENDIAN
  33. select SUPPORTS_CPU_MIPS32_R1
  34. select SUPPORTS_CPU_MIPS32_R2
  35. select SUPPORTS_CPU_MIPS32_R6
  36. select SUPPORTS_CPU_MIPS64_R1
  37. select SUPPORTS_CPU_MIPS64_R2
  38. select SUPPORTS_CPU_MIPS64_R6
  39. select SUPPORTS_LITTLE_ENDIAN
  40. select SWAP_IO_SPACE
  41. imply CMD_DM
  42. config TARGET_VCT
  43. bool "Support vct"
  44. select ROM_EXCEPTION_VECTORS
  45. select SUPPORTS_BIG_ENDIAN
  46. select SUPPORTS_CPU_MIPS32_R1
  47. select SUPPORTS_CPU_MIPS32_R2
  48. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  49. config ARCH_ATH79
  50. bool "Support QCA/Atheros ath79"
  51. select DM
  52. select OF_CONTROL
  53. imply CMD_DM
  54. config ARCH_MSCC
  55. bool "Support MSCC VCore-III"
  56. select OF_CONTROL
  57. select DM
  58. config ARCH_BMIPS
  59. bool "Support BMIPS SoCs"
  60. select CLK
  61. select CPU
  62. select DM
  63. select OF_CONTROL
  64. select RAM
  65. select SYSRESET
  66. imply CMD_DM
  67. config ARCH_MTMIPS
  68. bool "Support MediaTek MIPS platforms"
  69. select CLK
  70. imply CMD_DM
  71. select DISPLAY_CPUINFO
  72. select DM
  73. imply DM_ETH
  74. imply DM_GPIO
  75. select DM_RESET
  76. select DM_SERIAL
  77. select PINCTRL
  78. select PINMUX
  79. select PINCONF
  80. select RESET_MTMIPS
  81. imply DM_SPI
  82. imply DM_SPI_FLASH
  83. select LAST_STAGE_INIT
  84. select MIPS_TUNE_24KC
  85. select OF_CONTROL
  86. select ROM_EXCEPTION_VECTORS
  87. select SUPPORTS_CPU_MIPS32_R1
  88. select SUPPORTS_CPU_MIPS32_R2
  89. select SUPPORTS_LITTLE_ENDIAN
  90. select SYSRESET
  91. select SUPPORT_SPL
  92. config ARCH_JZ47XX
  93. bool "Support Ingenic JZ47xx"
  94. select SUPPORT_SPL
  95. select OF_CONTROL
  96. select DM
  97. config MACH_PIC32
  98. bool "Support Microchip PIC32"
  99. select DM
  100. select OF_CONTROL
  101. imply CMD_DM
  102. config TARGET_BOSTON
  103. bool "Support Boston"
  104. select DM
  105. select DM_SERIAL
  106. select MIPS_CM
  107. select MIPS_L1_CACHE_SHIFT_6
  108. select MIPS_L2_CACHE
  109. select OF_BOARD_SETUP
  110. select OF_CONTROL
  111. select ROM_EXCEPTION_VECTORS
  112. select SUPPORTS_BIG_ENDIAN
  113. select SUPPORTS_CPU_MIPS32_R1
  114. select SUPPORTS_CPU_MIPS32_R2
  115. select SUPPORTS_CPU_MIPS32_R6
  116. select SUPPORTS_CPU_MIPS64_R1
  117. select SUPPORTS_CPU_MIPS64_R2
  118. select SUPPORTS_CPU_MIPS64_R6
  119. select SUPPORTS_LITTLE_ENDIAN
  120. imply CMD_DM
  121. config TARGET_XILFPGA
  122. bool "Support Imagination Xilfpga"
  123. select DM
  124. select DM_ETH
  125. select DM_GPIO
  126. select DM_SERIAL
  127. select MIPS_L1_CACHE_SHIFT_4
  128. select OF_CONTROL
  129. select ROM_EXCEPTION_VECTORS
  130. select SUPPORTS_CPU_MIPS32_R1
  131. select SUPPORTS_CPU_MIPS32_R2
  132. select SUPPORTS_LITTLE_ENDIAN
  133. imply CMD_DM
  134. help
  135. This supports IMGTEC MIPSfpga platform
  136. endchoice
  137. source "board/imgtec/boston/Kconfig"
  138. source "board/imgtec/malta/Kconfig"
  139. source "board/imgtec/xilfpga/Kconfig"
  140. source "board/qemu-mips/Kconfig"
  141. source "arch/mips/mach-ath79/Kconfig"
  142. source "arch/mips/mach-mscc/Kconfig"
  143. source "arch/mips/mach-bmips/Kconfig"
  144. source "arch/mips/mach-jz47xx/Kconfig"
  145. source "arch/mips/mach-pic32/Kconfig"
  146. source "arch/mips/mach-mtmips/Kconfig"
  147. if MIPS
  148. choice
  149. prompt "Endianness selection"
  150. help
  151. Some MIPS boards can be configured for either little or big endian
  152. byte order. These modes require different U-Boot images. In general there
  153. is one preferred byteorder for a particular system but some systems are
  154. just as commonly used in the one or the other endianness.
  155. config SYS_BIG_ENDIAN
  156. bool "Big endian"
  157. depends on SUPPORTS_BIG_ENDIAN
  158. config SYS_LITTLE_ENDIAN
  159. bool "Little endian"
  160. depends on SUPPORTS_LITTLE_ENDIAN
  161. endchoice
  162. choice
  163. prompt "CPU selection"
  164. default CPU_MIPS32_R2
  165. config CPU_MIPS32_R1
  166. bool "MIPS32 Release 1"
  167. depends on SUPPORTS_CPU_MIPS32_R1
  168. select 32BIT
  169. help
  170. Choose this option to build an U-Boot for release 1 through 5 of the
  171. MIPS32 architecture.
  172. config CPU_MIPS32_R2
  173. bool "MIPS32 Release 2"
  174. depends on SUPPORTS_CPU_MIPS32_R2
  175. select 32BIT
  176. help
  177. Choose this option to build an U-Boot for release 2 through 5 of the
  178. MIPS32 architecture.
  179. config CPU_MIPS32_R6
  180. bool "MIPS32 Release 6"
  181. depends on SUPPORTS_CPU_MIPS32_R6
  182. select 32BIT
  183. help
  184. Choose this option to build an U-Boot for release 6 or later of the
  185. MIPS32 architecture.
  186. config CPU_MIPS64_R1
  187. bool "MIPS64 Release 1"
  188. depends on SUPPORTS_CPU_MIPS64_R1
  189. select 64BIT
  190. help
  191. Choose this option to build a kernel for release 1 through 5 of the
  192. MIPS64 architecture.
  193. config CPU_MIPS64_R2
  194. bool "MIPS64 Release 2"
  195. depends on SUPPORTS_CPU_MIPS64_R2
  196. select 64BIT
  197. help
  198. Choose this option to build a kernel for release 2 through 5 of the
  199. MIPS64 architecture.
  200. config CPU_MIPS64_R6
  201. bool "MIPS64 Release 6"
  202. depends on SUPPORTS_CPU_MIPS64_R6
  203. select 64BIT
  204. help
  205. Choose this option to build a kernel for release 6 or later of the
  206. MIPS64 architecture.
  207. endchoice
  208. menu "General setup"
  209. config ROM_EXCEPTION_VECTORS
  210. bool "Build U-Boot image with exception vectors"
  211. help
  212. Enable this to include exception vectors in the U-Boot image. This is
  213. required if the U-Boot entry point is equal to the address of the
  214. CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
  215. U-Boot booted from parallel NOR flash).
  216. Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
  217. In that case the image size will be reduced by 0x500 bytes.
  218. config MIPS_CM_BASE
  219. hex "MIPS CM GCR Base Address"
  220. depends on MIPS_CM
  221. default 0x16100000 if TARGET_BOSTON
  222. default 0x1fbf8000
  223. help
  224. The physical base address at which to map the MIPS Coherence Manager
  225. Global Configuration Registers (GCRs). This should be set such that
  226. the GCRs occupy a region of the physical address space which is
  227. otherwise unused, or at minimum that software doesn't need to access.
  228. config MIPS_CACHE_INDEX_BASE
  229. hex "Index base address for cache initialisation"
  230. default 0x80000000 if CPU_MIPS32
  231. default 0xffffffff80000000 if CPU_MIPS64
  232. help
  233. This is the base address for a memory block, which is used for
  234. initialising the cache lines. This is also the base address of a memory
  235. block which is used for loading and filling cache lines when
  236. SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
  237. Normally this is CKSEG0. If the MIPS system needs to move this block
  238. to some SRAM or ScratchPad RAM, adapt this option accordingly.
  239. config MIPS_RELOCATION_TABLE_SIZE
  240. hex "Relocation table size"
  241. range 0x100 0x10000
  242. default "0x8000"
  243. ---help---
  244. A table of relocation data will be appended to the U-Boot binary
  245. and parsed in relocate_code() to fix up all offsets in the relocated
  246. U-Boot.
  247. This option allows the amount of space reserved for the table to be
  248. adjusted in a range from 256 up to 64k. The default is 32k and should
  249. be ok in most cases. Reduce this value to shrink the size of U-Boot
  250. binary.
  251. The build will fail and a valid size suggested if this is too small.
  252. If unsure, leave at the default value.
  253. config RESTORE_EXCEPTION_VECTOR_BASE
  254. bool "Restore exception vector base before booting linux kernel"
  255. default n
  256. help
  257. In U-Boot the exception vector base will be moved to top of memory,
  258. to be used to display register dump when exception occurs.
  259. But some old linux kernel does not honor the base set in CP0_EBASE.
  260. A modified exception vector base will cause kernel crash.
  261. This option will restore the exception vector base to its previous
  262. value.
  263. If unsure, say N.
  264. config OVERRIDE_EXCEPTION_VECTOR_BASE
  265. bool "Override the exception vector base to be restored"
  266. depends on RESTORE_EXCEPTION_VECTOR_BASE
  267. default n
  268. help
  269. Enable this option if you want to use a different exception vector
  270. base rather than the previously saved one.
  271. config NEW_EXCEPTION_VECTOR_BASE
  272. hex "New exception vector base"
  273. depends on OVERRIDE_EXCEPTION_VECTOR_BASE
  274. range 0x80000000 0xbffff000
  275. default 0x80000000
  276. help
  277. The exception vector base to be restored before booting linux kernel
  278. config INIT_STACK_WITHOUT_MALLOC_F
  279. bool "Do not reserve malloc space on initial stack"
  280. default n
  281. help
  282. Enable this option if you don't want to reserve malloc space on
  283. initial stack. This is useful if the initial stack can't hold large
  284. malloc space. Platform should set the malloc_base later when DRAM is
  285. ready to use.
  286. config SPL_INIT_STACK_WITHOUT_MALLOC_F
  287. bool "Do not reserve malloc space on initial stack in SPL"
  288. default n
  289. help
  290. Enable this option if you don't want to reserve malloc space on
  291. initial stack. This is useful if the initial stack can't hold large
  292. malloc space. Platform should set the malloc_base later when DRAM is
  293. ready to use.
  294. config SPL_LOADER_SUPPORT
  295. bool
  296. default n
  297. help
  298. Enable this option if you want to use SPL loaders without DM enabled.
  299. endmenu
  300. menu "OS boot interface"
  301. config MIPS_BOOT_CMDLINE_LEGACY
  302. bool "Hand over legacy command line to Linux kernel"
  303. default y
  304. help
  305. Enable this option if you want U-Boot to hand over the Yamon-style
  306. command line to the kernel. All bootargs will be prepared as argc/argv
  307. compatible list. The argument count (argc) is stored in register $a0.
  308. The address of the argument list (argv) is stored in register $a1.
  309. config MIPS_BOOT_ENV_LEGACY
  310. bool "Hand over legacy environment to Linux kernel"
  311. default y
  312. help
  313. Enable this option if you want U-Boot to hand over the Yamon-style
  314. environment to the kernel. Information like memory size, initrd
  315. address and size will be prepared as zero-terminated key/value list.
  316. The address of the environment is stored in register $a2.
  317. config MIPS_BOOT_FDT
  318. bool "Hand over a flattened device tree to Linux kernel"
  319. default n
  320. help
  321. Enable this option if you want U-Boot to hand over a flattened
  322. device tree to the kernel. According to UHI register $a0 will be set
  323. to -2 and the FDT address is stored in $a1.
  324. endmenu
  325. config SUPPORTS_BIG_ENDIAN
  326. bool
  327. config SUPPORTS_LITTLE_ENDIAN
  328. bool
  329. config SUPPORTS_CPU_MIPS32_R1
  330. bool
  331. config SUPPORTS_CPU_MIPS32_R2
  332. bool
  333. config SUPPORTS_CPU_MIPS32_R6
  334. bool
  335. config SUPPORTS_CPU_MIPS64_R1
  336. bool
  337. config SUPPORTS_CPU_MIPS64_R2
  338. bool
  339. config SUPPORTS_CPU_MIPS64_R6
  340. bool
  341. config CPU_MIPS32
  342. bool
  343. default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
  344. config CPU_MIPS64
  345. bool
  346. default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
  347. config MIPS_TUNE_4KC
  348. bool
  349. config MIPS_TUNE_14KC
  350. bool
  351. config MIPS_TUNE_24KC
  352. bool
  353. config MIPS_TUNE_34KC
  354. bool
  355. config MIPS_TUNE_74KC
  356. bool
  357. config 32BIT
  358. bool
  359. config 64BIT
  360. bool
  361. config SWAP_IO_SPACE
  362. bool
  363. config SYS_MIPS_CACHE_INIT_RAM_LOAD
  364. bool
  365. config MIPS_INIT_STACK_IN_SRAM
  366. bool
  367. default n
  368. help
  369. Select this if the initial stack frame could be setup in SRAM.
  370. Normally the initial stack frame is set up in DRAM which is often
  371. only available after lowlevel_init. With this option the initial
  372. stack frame and the early C environment is set up before
  373. lowlevel_init. Thus lowlevel_init does not need to be implemented
  374. in assembler.
  375. config MIPS_SRAM_INIT
  376. bool
  377. default n
  378. depends on MIPS_INIT_STACK_IN_SRAM
  379. help
  380. Select this if the SRAM for initial stack needs to be initialized
  381. before it can be used. If enabled, a function mips_sram_init() will
  382. be called just before setup_stack_gd.
  383. config SYS_DCACHE_SIZE
  384. int
  385. default 0
  386. help
  387. The total size of the L1 Dcache, if known at compile time.
  388. config SYS_DCACHE_LINE_SIZE
  389. int
  390. default 0
  391. help
  392. The size of L1 Dcache lines, if known at compile time.
  393. config SYS_ICACHE_SIZE
  394. int
  395. default 0
  396. help
  397. The total size of the L1 ICache, if known at compile time.
  398. config SYS_ICACHE_LINE_SIZE
  399. int
  400. default 0
  401. help
  402. The size of L1 Icache lines, if known at compile time.
  403. config SYS_SCACHE_LINE_SIZE
  404. int
  405. default 0
  406. help
  407. The size of L2 cache lines, if known at compile time.
  408. config SYS_CACHE_SIZE_AUTO
  409. def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
  410. SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
  411. SYS_SCACHE_LINE_SIZE = 0
  412. help
  413. Select this (or let it be auto-selected by not defining any cache
  414. sizes) in order to allow U-Boot to automatically detect the sizes
  415. of caches at runtime. This has a small cost in code size & runtime
  416. so if you know the cache configuration for your system at compile
  417. time it would be beneficial to configure it.
  418. config MIPS_L1_CACHE_SHIFT_4
  419. bool
  420. config MIPS_L1_CACHE_SHIFT_5
  421. bool
  422. config MIPS_L1_CACHE_SHIFT_6
  423. bool
  424. config MIPS_L1_CACHE_SHIFT_7
  425. bool
  426. config MIPS_L1_CACHE_SHIFT
  427. int
  428. default "7" if MIPS_L1_CACHE_SHIFT_7
  429. default "6" if MIPS_L1_CACHE_SHIFT_6
  430. default "5" if MIPS_L1_CACHE_SHIFT_5
  431. default "4" if MIPS_L1_CACHE_SHIFT_4
  432. default "5"
  433. config MIPS_L2_CACHE
  434. bool
  435. help
  436. Select this if your system includes an L2 cache and you want U-Boot
  437. to initialise & maintain it.
  438. config DYNAMIC_IO_PORT_BASE
  439. bool
  440. config MIPS_CM
  441. bool
  442. help
  443. Select this if your system contains a MIPS Coherence Manager and you
  444. wish U-Boot to configure it or make use of it to retrieve system
  445. information such as cache configuration.
  446. config MIPS_INSERT_BOOT_CONFIG
  447. bool
  448. default n
  449. help
  450. Enable this to insert some board-specific boot configuration in
  451. the U-Boot binary at offset 0x10.
  452. config MIPS_BOOT_CONFIG_WORD0
  453. hex
  454. depends on MIPS_INSERT_BOOT_CONFIG
  455. default 0x420 if TARGET_MALTA
  456. default 0x0
  457. help
  458. Value which is inserted as boot config word 0.
  459. config MIPS_BOOT_CONFIG_WORD1
  460. hex
  461. depends on MIPS_INSERT_BOOT_CONFIG
  462. default 0x0
  463. help
  464. Value which is inserted as boot config word 1.
  465. endif
  466. endmenu