m53menlo.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Menlosystems M53Menlo board
  4. *
  5. * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
  6. * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/iomux-mx53.h>
  18. #include <asm/mach-imx/mx5_video.h>
  19. #include <asm/mach-imx/video.h>
  20. #include <asm/gpio.h>
  21. #include <asm/spl.h>
  22. #include <env.h>
  23. #include <fdt_support.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <gzip.h>
  26. #include <i2c.h>
  27. #include <ipu_pixfmt.h>
  28. #include <linux/errno.h>
  29. #include <linux/fb.h>
  30. #include <mmc.h>
  31. #include <netdev.h>
  32. #include <spl.h>
  33. #include <splash.h>
  34. #include <usb/ehci-ci.h>
  35. #include <video_console.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static u32 mx53_dram_size[2];
  38. ulong board_get_usable_ram_top(ulong total_size)
  39. {
  40. /*
  41. * WARNING: We must override get_effective_memsize() function here
  42. * to report only the size of the first DRAM bank. This is to make
  43. * U-Boot relocator place U-Boot into valid memory, that is, at the
  44. * end of the first DRAM bank. If we did not override this function
  45. * like so, U-Boot would be placed at the address of the first DRAM
  46. * bank + total DRAM size - sizeof(uboot), which in the setup where
  47. * each DRAM bank contains 512MiB of DRAM would result in placing
  48. * U-Boot into invalid memory area close to the end of the first
  49. * DRAM bank.
  50. */
  51. return PHYS_SDRAM_2 + mx53_dram_size[1];
  52. }
  53. int dram_init(void)
  54. {
  55. mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  56. mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  57. gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  58. return 0;
  59. }
  60. int dram_init_banksize(void)
  61. {
  62. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  63. gd->bd->bi_dram[0].size = mx53_dram_size[0];
  64. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  65. gd->bd->bi_dram[1].size = mx53_dram_size[1];
  66. return 0;
  67. }
  68. static void setup_iomux_uart(void)
  69. {
  70. static const iomux_v3_cfg_t uart_pads[] = {
  71. MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  72. MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  73. };
  74. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  75. }
  76. static void setup_iomux_fec(void)
  77. {
  78. static const iomux_v3_cfg_t fec_pads[] = {
  79. /* MDIO pads */
  80. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  81. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  82. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  83. /* FEC 0 pads */
  84. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  85. PAD_CTL_HYS | PAD_CTL_PKE),
  86. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  87. PAD_CTL_HYS | PAD_CTL_PKE),
  88. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  89. PAD_CTL_HYS | PAD_CTL_PKE),
  90. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  91. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  92. PAD_CTL_HYS | PAD_CTL_PKE),
  93. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  94. PAD_CTL_HYS | PAD_CTL_PKE),
  95. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  96. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  97. /* FEC 1 pads */
  98. NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
  99. PAD_CTL_HYS | PAD_CTL_PKE),
  100. NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
  101. PAD_CTL_HYS | PAD_CTL_PKE),
  102. NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
  103. PAD_CTL_HYS | PAD_CTL_PKE),
  104. NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
  105. PAD_CTL_HYS | PAD_CTL_PKE),
  106. NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
  107. PAD_CTL_HYS | PAD_CTL_PKE),
  108. NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
  109. NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
  110. PAD_CTL_HYS | PAD_CTL_PKE),
  111. NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
  112. };
  113. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  114. }
  115. #ifdef CONFIG_FSL_ESDHC_IMX
  116. struct fsl_esdhc_cfg esdhc_cfg = {
  117. MMC_SDHC1_BASE_ADDR,
  118. };
  119. int board_mmc_getcd(struct mmc *mmc)
  120. {
  121. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
  122. gpio_direction_input(IMX_GPIO_NR(1, 1));
  123. return !gpio_get_value(IMX_GPIO_NR(1, 1));
  124. }
  125. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  126. PAD_CTL_PUS_100K_UP)
  127. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  128. PAD_CTL_DSE_HIGH)
  129. int board_mmc_init(bd_t *bis)
  130. {
  131. static const iomux_v3_cfg_t sd1_pads[] = {
  132. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  133. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  134. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  135. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  136. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  137. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  138. };
  139. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  140. imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
  141. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  142. }
  143. #endif
  144. static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
  145. {
  146. static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  147. int ret;
  148. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  149. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  150. /*
  151. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  152. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  153. */
  154. ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
  155. if (ret)
  156. puts("IPU: Failed to configure LDB clock\n");
  157. /* Configure CCM_CSCMR2 */
  158. clrsetbits_le32(&mxc_ccm->cscmr2,
  159. (0x7 << 26) | BIT(10) | BIT(8),
  160. (0x5 << 26) | BIT(10) | BIT(8));
  161. /* Configure LDB_CTRL */
  162. writel(0x201, 0x53fa8008);
  163. }
  164. static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
  165. {
  166. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  167. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  168. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  169. /*
  170. * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
  171. * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  172. */
  173. enable_lvds_clock(dev, 63);
  174. }
  175. static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
  176. {
  177. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  178. /*
  179. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  180. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  181. */
  182. enable_lvds_clock(dev, 233);
  183. /* For ETM0700G0DH6 model, this may be enabled after the clock. */
  184. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  185. }
  186. static const char *lvds_compat_string;
  187. static int detect_lvds(struct display_info_t const *dev)
  188. {
  189. u8 touchid[23];
  190. u8 *touchptr = &touchid[0];
  191. int ret;
  192. ret = i2c_set_bus_num(0);
  193. if (ret)
  194. return 0;
  195. /* Touchscreen is at address 0x38, ID register is 0xbb. */
  196. ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
  197. if (ret)
  198. return 0;
  199. /* EP0430 prefixes the response with 0xbb, skip it. */
  200. if (*touchptr == 0xbb)
  201. touchptr++;
  202. /* Skip the 'EP' prefix. */
  203. touchptr += 2;
  204. ret = !memcmp(touchptr, &dev->mode.name[7], 4);
  205. if (ret)
  206. lvds_compat_string = dev->mode.name;
  207. return ret;
  208. }
  209. void board_preboot_os(void)
  210. {
  211. /* Power off the LCD to prevent awful color flicker */
  212. gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
  213. }
  214. int ft_board_setup(void *blob, bd_t *bd)
  215. {
  216. if (lvds_compat_string)
  217. do_fixup_by_path_string(blob, "/panel", "compatible",
  218. lvds_compat_string);
  219. return 0;
  220. }
  221. struct display_info_t const displays[] = {
  222. {
  223. .bus = 0,
  224. .addr = 0,
  225. .detect = detect_lvds,
  226. .enable = enable_lvds_etm0430g0dh6,
  227. .pixfmt = IPU_PIX_FMT_RGB666,
  228. .mode = {
  229. .name = "edt,etm0430g0dh6",
  230. .refresh = 60,
  231. .xres = 480,
  232. .yres = 272,
  233. .pixclock = 111111, /* picosecond (9 MHz) */
  234. .left_margin = 2,
  235. .right_margin = 2,
  236. .upper_margin = 2,
  237. .lower_margin = 2,
  238. .hsync_len = 41,
  239. .vsync_len = 10,
  240. .sync = 0x40000000,
  241. .vmode = FB_VMODE_NONINTERLACED
  242. }
  243. }, {
  244. .bus = 0,
  245. .addr = 0,
  246. .detect = detect_lvds,
  247. .enable = enable_lvds_etm0700g0dh6,
  248. .pixfmt = IPU_PIX_FMT_RGB666,
  249. .mode = {
  250. .name = "edt,etm0700g0dh6",
  251. .refresh = 60,
  252. .xres = 800,
  253. .yres = 480,
  254. .pixclock = 30048, /* picosecond (33.28 MHz) */
  255. .left_margin = 40,
  256. .right_margin = 88,
  257. .upper_margin = 10,
  258. .lower_margin = 33,
  259. .hsync_len = 128,
  260. .vsync_len = 2,
  261. .sync = FB_SYNC_EXT,
  262. .vmode = FB_VMODE_NONINTERLACED
  263. }
  264. }
  265. };
  266. size_t display_count = ARRAY_SIZE(displays);
  267. #ifdef CONFIG_SPLASH_SCREEN
  268. static struct splash_location default_splash_locations[] = {
  269. {
  270. .name = "mmc_fs",
  271. .storage = SPLASH_STORAGE_MMC,
  272. .flags = SPLASH_STORAGE_FS,
  273. .devpart = "0:1",
  274. },
  275. };
  276. int splash_screen_prepare(void)
  277. {
  278. return splash_source_load(default_splash_locations,
  279. ARRAY_SIZE(default_splash_locations));
  280. }
  281. #endif
  282. int board_late_init(void)
  283. {
  284. #if defined(CONFIG_VIDEO_IPUV3)
  285. struct udevice *dev;
  286. int xpos, ypos, ret;
  287. char *s;
  288. void *dst;
  289. ulong addr, len;
  290. splash_get_pos(&xpos, &ypos);
  291. s = env_get("splashimage");
  292. if (!s)
  293. return 0;
  294. addr = simple_strtoul(s, NULL, 16);
  295. dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
  296. if (!dst)
  297. return -ENOMEM;
  298. ret = splash_screen_prepare();
  299. if (ret < 0)
  300. return ret;
  301. len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
  302. ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
  303. (uchar *)addr, &len);
  304. if (ret) {
  305. printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
  306. free(dst);
  307. return ret;
  308. }
  309. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  310. if (ret)
  311. return ret;
  312. ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
  313. if (ret)
  314. return ret;
  315. #endif
  316. return 0;
  317. }
  318. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  319. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  320. static void setup_iomux_i2c(void)
  321. {
  322. static const iomux_v3_cfg_t i2c_pads[] = {
  323. /* I2C1 */
  324. NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
  325. NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
  326. /* I2C2 */
  327. NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
  328. NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
  329. };
  330. imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  331. }
  332. static void setup_iomux_video(void)
  333. {
  334. static const iomux_v3_cfg_t lcd_pads[] = {
  335. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
  336. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
  337. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
  338. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
  339. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
  340. };
  341. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  342. }
  343. static void setup_iomux_nand(void)
  344. {
  345. static const iomux_v3_cfg_t nand_pads[] = {
  346. NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  347. PAD_CTL_DSE_HIGH),
  348. NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  349. PAD_CTL_DSE_HIGH),
  350. NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  351. PAD_CTL_DSE_HIGH),
  352. NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  353. PAD_CTL_DSE_HIGH),
  354. NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  355. PAD_CTL_PUS_100K_UP),
  356. NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  357. PAD_CTL_PUS_100K_UP),
  358. NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  359. PAD_CTL_DSE_HIGH),
  360. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
  361. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  362. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
  363. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  364. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
  365. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  366. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
  367. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  368. NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
  369. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  370. NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
  371. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  372. NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
  373. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  374. NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
  375. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  376. };
  377. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  378. }
  379. static void m53_set_clock(void)
  380. {
  381. int ret;
  382. const u32 ref_clk = MXC_HCLK;
  383. const u32 dramclk = 400;
  384. u32 cpuclk;
  385. gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
  386. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
  387. PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
  388. gpio_direction_input(IMX_GPIO_NR(4, 0));
  389. /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
  390. cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
  391. ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
  392. if (ret)
  393. printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
  394. ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
  395. if (ret) {
  396. printf("CPU: Switch peripheral clock to %dMHz failed\n",
  397. dramclk);
  398. }
  399. ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
  400. if (ret)
  401. printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
  402. }
  403. static void m53_set_nand(void)
  404. {
  405. u32 i;
  406. /* NAND flash is muxed on ATA pins */
  407. setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
  408. /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
  409. for (i = 0x4; i < 0x94; i += 0x18) {
  410. clrbits_le32(WEIM_BASE_ADDR + i,
  411. WEIM_GCR2_MUX16_BYP_GRANT_MASK);
  412. }
  413. mxc_set_clock(0, 33, MXC_NFC_CLK);
  414. enable_nfc_clk(1);
  415. }
  416. int board_early_init_f(void)
  417. {
  418. setup_iomux_uart();
  419. setup_iomux_fec();
  420. setup_iomux_i2c();
  421. setup_iomux_nand();
  422. setup_iomux_video();
  423. m53_set_clock();
  424. mxc_set_sata_internal_clock();
  425. /* NAND clock @ 33MHz */
  426. m53_set_nand();
  427. return 0;
  428. }
  429. int board_init(void)
  430. {
  431. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  432. return 0;
  433. }
  434. int checkboard(void)
  435. {
  436. puts("Board: Menlosystems M53Menlo\n");
  437. return 0;
  438. }
  439. /*
  440. * NAND SPL
  441. */
  442. #ifdef CONFIG_SPL_BUILD
  443. void spl_board_init(void)
  444. {
  445. setup_iomux_nand();
  446. m53_set_clock();
  447. m53_set_nand();
  448. }
  449. u32 spl_boot_device(void)
  450. {
  451. return BOOT_DEVICE_NAND;
  452. }
  453. #endif