board.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
  4. *
  5. * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <serial.h>
  13. #include <spl.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/omap.h>
  17. #include <asm/arch/ddr_defs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/mmc_host_def.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/io.h>
  23. #include <asm/emif.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <cpsw.h>
  28. #include <fdt_support.h>
  29. #include <mtd_node.h>
  30. #include <jffs2/load_kernel.h>
  31. #include "board.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  34. * and control IGEP0034 green and red LEDs.
  35. * U-boot configures these pins as input pullup to detect board revision:
  36. * IGEP0034-LITE = 0b00
  37. * IGEP0034 (FULL) = 0b01
  38. * IGEP0033 = 0b1X
  39. */
  40. #define GPIO_GREEN_REVISION 27
  41. #define GPIO_RED_REVISION 26
  42. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  43. /*
  44. * Routine: get_board_revision
  45. * Description: Returns the board revision
  46. */
  47. static int get_board_revision(void)
  48. {
  49. int revision;
  50. gpio_request(GPIO_GREEN_REVISION, "green_revision");
  51. gpio_direction_input(GPIO_GREEN_REVISION);
  52. revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  53. gpio_free(GPIO_GREEN_REVISION);
  54. gpio_request(GPIO_RED_REVISION, "red_revision");
  55. gpio_direction_input(GPIO_RED_REVISION);
  56. revision = revision + gpio_get_value(GPIO_RED_REVISION);
  57. gpio_free(GPIO_RED_REVISION);
  58. return revision;
  59. }
  60. #ifdef CONFIG_SPL_BUILD
  61. /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  62. static const struct ddr_data ddr3_igep0034_data = {
  63. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  64. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  65. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  66. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  67. };
  68. static const struct ddr_data ddr3_igep0034_lite_data = {
  69. .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  70. .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  71. .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  72. .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  73. };
  74. static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  75. .cmd0csratio = MT41K256M16HA125E_RATIO,
  76. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  77. .cmd1csratio = MT41K256M16HA125E_RATIO,
  78. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  79. .cmd2csratio = MT41K256M16HA125E_RATIO,
  80. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  81. };
  82. static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  83. .cmd0csratio = K4B2G1646EBIH9_RATIO,
  84. .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  85. .cmd1csratio = K4B2G1646EBIH9_RATIO,
  86. .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  87. .cmd2csratio = K4B2G1646EBIH9_RATIO,
  88. .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  89. };
  90. static struct emif_regs ddr3_igep0034_emif_reg_data = {
  91. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  92. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  93. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  94. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  95. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  96. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  97. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  98. };
  99. static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
  100. .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  101. .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  102. .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  103. .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  104. .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  105. .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  106. .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  107. };
  108. const struct ctrl_ioregs ioregs_igep0034 = {
  109. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  110. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  111. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  112. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  113. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  114. };
  115. const struct ctrl_ioregs ioregs_igep0034_lite = {
  116. .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  117. .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  118. .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  119. .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  120. .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  121. };
  122. #define OSC (V_OSCK/1000000)
  123. const struct dpll_params dpll_ddr = {
  124. 400, OSC-1, 1, -1, -1, -1, -1};
  125. const struct dpll_params *get_dpll_ddr_params(void)
  126. {
  127. return &dpll_ddr;
  128. }
  129. void set_uart_mux_conf(void)
  130. {
  131. enable_uart0_pin_mux();
  132. }
  133. void set_mux_conf_regs(void)
  134. {
  135. enable_board_pin_mux();
  136. }
  137. void sdram_init(void)
  138. {
  139. if (get_board_revision() == 1)
  140. config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
  141. &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
  142. else
  143. config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
  144. &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
  145. }
  146. #ifdef CONFIG_SPL_OS_BOOT
  147. int spl_start_uboot(void)
  148. {
  149. /* break into full u-boot on 'c' */
  150. return serial_tstc() && serial_getc() == 'c';
  151. }
  152. #endif
  153. #endif
  154. /*
  155. * Basic board specific setup. Pinmux has been handled already.
  156. */
  157. int board_init(void)
  158. {
  159. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  160. gpmc_init();
  161. return 0;
  162. }
  163. #ifdef CONFIG_BOARD_LATE_INIT
  164. int board_late_init(void)
  165. {
  166. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  167. switch (get_board_revision()) {
  168. case 0:
  169. env_set("board_name", "igep0034-lite");
  170. break;
  171. case 1:
  172. env_set("board_name", "igep0034");
  173. break;
  174. default:
  175. env_set("board_name", "igep0033");
  176. break;
  177. }
  178. #endif
  179. return 0;
  180. }
  181. #endif
  182. #ifdef CONFIG_OF_BOARD_SETUP
  183. int ft_board_setup(void *blob, bd_t *bd)
  184. {
  185. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  186. static const struct node_info nodes[] = {
  187. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  188. };
  189. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  190. #endif
  191. return 0;
  192. }
  193. #endif
  194. #if defined(CONFIG_DRIVER_TI_CPSW)
  195. static void cpsw_control(int enabled)
  196. {
  197. /* VTP can be added here */
  198. return;
  199. }
  200. static struct cpsw_slave_data cpsw_slaves[] = {
  201. {
  202. .slave_reg_ofs = 0x208,
  203. .sliver_reg_ofs = 0xd80,
  204. .phy_addr = 0,
  205. .phy_if = PHY_INTERFACE_MODE_RMII,
  206. },
  207. };
  208. static struct cpsw_platform_data cpsw_data = {
  209. .mdio_base = CPSW_MDIO_BASE,
  210. .cpsw_base = CPSW_BASE,
  211. .mdio_div = 0xff,
  212. .channels = 8,
  213. .cpdma_reg_ofs = 0x800,
  214. .slaves = 1,
  215. .slave_data = cpsw_slaves,
  216. .ale_reg_ofs = 0xd00,
  217. .ale_entries = 1024,
  218. .host_port_reg_ofs = 0x108,
  219. .hw_stats_reg_ofs = 0x900,
  220. .bd_ram_ofs = 0x2000,
  221. .mac_control = (1 << 5),
  222. .control = cpsw_control,
  223. .host_port_num = 0,
  224. .version = CPSW_CTRL_VERSION_2,
  225. };
  226. int board_eth_init(bd_t *bis)
  227. {
  228. int rv, ret = 0;
  229. uint8_t mac_addr[6];
  230. uint32_t mac_hi, mac_lo;
  231. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  232. /* try reading mac address from efuse */
  233. mac_lo = readl(&cdev->macid0l);
  234. mac_hi = readl(&cdev->macid0h);
  235. mac_addr[0] = mac_hi & 0xFF;
  236. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  237. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  238. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  239. mac_addr[4] = mac_lo & 0xFF;
  240. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  241. if (is_valid_ethaddr(mac_addr))
  242. eth_env_set_enetaddr("ethaddr", mac_addr);
  243. }
  244. writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
  245. &cdev->miisel);
  246. if (get_board_revision() == 1)
  247. cpsw_slaves[0].phy_addr = 1;
  248. rv = cpsw_register(&cpsw_data);
  249. if (rv < 0)
  250. printf("Error %d registering CPSW switch\n", rv);
  251. else
  252. ret += rv;
  253. return ret;
  254. }
  255. #endif