mrccache.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/southbridge/intel/bd82x6x/mrccache.c
  4. *
  5. * Copyright (C) 2014 Google Inc.
  6. * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <spi.h>
  15. #include <spi_flash.h>
  16. #include <asm/mrccache.h>
  17. #include <dm/device-internal.h>
  18. #include <dm/uclass-internal.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static uint mrc_block_size(uint data_size)
  21. {
  22. uint mrc_size = sizeof(struct mrc_data_container) + data_size;
  23. return ALIGN(mrc_size, MRC_DATA_ALIGN);
  24. }
  25. static struct mrc_data_container *next_mrc_block(
  26. struct mrc_data_container *cache)
  27. {
  28. /* MRC data blocks are aligned within the region */
  29. u8 *region_ptr = (u8 *)cache;
  30. region_ptr += mrc_block_size(cache->data_size);
  31. return (struct mrc_data_container *)region_ptr;
  32. }
  33. static int is_mrc_cache(struct mrc_data_container *cache)
  34. {
  35. return cache && (cache->signature == MRC_DATA_SIGNATURE);
  36. }
  37. struct mrc_data_container *mrccache_find_current(struct mrc_region *entry)
  38. {
  39. struct mrc_data_container *cache, *next;
  40. ulong base_addr, end_addr;
  41. uint id;
  42. base_addr = entry->base + entry->offset;
  43. end_addr = base_addr + entry->length;
  44. cache = NULL;
  45. /* Search for the last filled entry in the region */
  46. for (id = 0, next = (struct mrc_data_container *)base_addr;
  47. is_mrc_cache(next);
  48. id++) {
  49. cache = next;
  50. next = next_mrc_block(next);
  51. if ((ulong)next >= end_addr)
  52. break;
  53. }
  54. if (id-- == 0) {
  55. debug("%s: No valid MRC cache found.\n", __func__);
  56. return NULL;
  57. }
  58. /* Verify checksum */
  59. if (cache->checksum != compute_ip_checksum(cache->data,
  60. cache->data_size)) {
  61. printf("%s: MRC cache checksum mismatch\n", __func__);
  62. return NULL;
  63. }
  64. debug("%s: picked entry %u from cache block\n", __func__, id);
  65. return cache;
  66. }
  67. /**
  68. * find_next_mrc_cache() - get next cache entry
  69. *
  70. * This moves to the next cache entry in the region, making sure it has enough
  71. * space to hold data of size @data_size.
  72. *
  73. * @entry: MRC cache flash area
  74. * @cache: Entry to start from
  75. * @data_size: Required data size of the new entry. Note that we assume that
  76. * all cache entries are the same size
  77. *
  78. * @return next cache entry if found, NULL if we got to the end
  79. */
  80. static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
  81. struct mrc_data_container *prev, int data_size)
  82. {
  83. struct mrc_data_container *cache;
  84. ulong base_addr, end_addr;
  85. base_addr = entry->base + entry->offset;
  86. end_addr = base_addr + entry->length;
  87. /*
  88. * We assume that all cache entries are the same size, but let's use
  89. * data_size here for clarity.
  90. */
  91. cache = next_mrc_block(prev);
  92. if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
  93. /* Crossed the boundary */
  94. cache = NULL;
  95. debug("%s: no available entries found\n", __func__);
  96. } else {
  97. debug("%s: picked next entry from cache block at %p\n",
  98. __func__, cache);
  99. }
  100. return cache;
  101. }
  102. /**
  103. * mrccache_update() - update the MRC cache with a new record
  104. *
  105. * This writes a new record to the end of the MRC cache region. If the new
  106. * record is the same as the latest record then the write is skipped
  107. *
  108. * @sf: SPI flash to write to
  109. * @entry: Position and size of MRC cache in SPI flash
  110. * @cur: Record to write
  111. * @return 0 if updated, -EEXIST if the record is the same as the latest
  112. * record, -EINVAL if the record is not valid, other error if SPI write failed
  113. */
  114. static int mrccache_update(struct udevice *sf, struct mrc_region *entry,
  115. struct mrc_data_container *cur)
  116. {
  117. struct mrc_data_container *cache;
  118. ulong offset;
  119. ulong base_addr;
  120. int ret;
  121. if (!is_mrc_cache(cur)) {
  122. debug("%s: Cache data not valid\n", __func__);
  123. return -EINVAL;
  124. }
  125. /* Find the last used block */
  126. base_addr = entry->base + entry->offset;
  127. debug("Updating MRC cache data\n");
  128. cache = mrccache_find_current(entry);
  129. if (cache && (cache->data_size == cur->data_size) &&
  130. (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
  131. debug("MRC data in flash is up to date. No update\n");
  132. return -EEXIST;
  133. }
  134. /* Move to the next block, which will be the first unused block */
  135. if (cache)
  136. cache = find_next_mrc_cache(entry, cache, cur->data_size);
  137. /*
  138. * If we have got to the end, erase the entire mrc-cache area and start
  139. * again at block 0.
  140. */
  141. if (!cache) {
  142. debug("Erasing the MRC cache region of %x bytes at %x\n",
  143. entry->length, entry->offset);
  144. ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
  145. if (ret) {
  146. debug("Failed to erase flash region\n");
  147. return ret;
  148. }
  149. cache = (struct mrc_data_container *)base_addr;
  150. }
  151. /* Write the data out */
  152. offset = (ulong)cache - base_addr + entry->offset;
  153. debug("Write MRC cache update to flash at %lx\n", offset);
  154. ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
  155. cur);
  156. if (ret) {
  157. debug("Failed to write to SPI flash\n");
  158. return log_msg_ret("Cannot update mrccache", ret);
  159. }
  160. return 0;
  161. }
  162. static void mrccache_setup(struct mrc_output *mrc, void *data)
  163. {
  164. struct mrc_data_container *cache = data;
  165. u16 checksum;
  166. cache->signature = MRC_DATA_SIGNATURE;
  167. cache->data_size = mrc->len;
  168. checksum = compute_ip_checksum(mrc->buf, cache->data_size);
  169. debug("Saving %d bytes for MRC output data, checksum %04x\n",
  170. cache->data_size, checksum);
  171. cache->checksum = checksum;
  172. cache->reserved = 0;
  173. memcpy(cache->data, mrc->buf, cache->data_size);
  174. mrc->cache = cache;
  175. }
  176. int mrccache_reserve(void)
  177. {
  178. int i;
  179. for (i = 0; i < MRC_TYPE_COUNT; i++) {
  180. struct mrc_output *mrc = &gd->arch.mrc[i];
  181. if (!mrc->len)
  182. continue;
  183. /* adjust stack pointer to store pure cache data plus header */
  184. gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE);
  185. mrccache_setup(mrc, (void *)gd->start_addr_sp);
  186. gd->start_addr_sp &= ~0xf;
  187. }
  188. return 0;
  189. }
  190. int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
  191. struct mrc_region *entry)
  192. {
  193. struct udevice *dev;
  194. ofnode mrc_node;
  195. ulong map_base;
  196. uint map_size;
  197. uint offset;
  198. u32 reg[2];
  199. int ret;
  200. /*
  201. * Find the flash chip within the SPI controller node. Avoid probing
  202. * the device here since it may put it into a strange state where the
  203. * memory map cannot be read.
  204. */
  205. ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
  206. if (ret)
  207. return log_msg_ret("Cannot find SPI flash\n", ret);
  208. ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
  209. if (!ret) {
  210. entry->base = map_base;
  211. } else {
  212. ret = dev_read_u32_array(dev, "memory-map", reg, 2);
  213. if (ret)
  214. return log_msg_ret("Cannot find memory map\n", ret);
  215. entry->base = reg[0];
  216. }
  217. /* Find the place where we put the MRC cache */
  218. mrc_node = dev_read_subnode(dev, type == MRC_TYPE_NORMAL ?
  219. "rw-mrc-cache" : "rw-var-mrc-cache");
  220. if (!ofnode_valid(mrc_node))
  221. return log_msg_ret("Cannot find node", -EPERM);
  222. ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
  223. if (ret)
  224. return log_msg_ret("Cannot find address", ret);
  225. entry->offset = reg[0];
  226. entry->length = reg[1];
  227. if (devp)
  228. *devp = dev;
  229. debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
  230. type, dev->name, entry->offset, entry->length, entry->base);
  231. return 0;
  232. }
  233. static int mrccache_save_type(enum mrc_type_t type)
  234. {
  235. struct mrc_data_container *cache;
  236. struct mrc_output *mrc;
  237. struct mrc_region entry;
  238. struct udevice *sf;
  239. int ret;
  240. mrc = &gd->arch.mrc[type];
  241. if (!mrc->len)
  242. return 0;
  243. log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
  244. mrc->len, type);
  245. ret = mrccache_get_region(type, &sf, &entry);
  246. if (ret)
  247. return log_msg_ret("Cannot get region", ret);
  248. ret = device_probe(sf);
  249. if (ret)
  250. return log_msg_ret("Cannot probe device", ret);
  251. cache = mrc->cache;
  252. ret = mrccache_update(sf, &entry, cache);
  253. if (!ret)
  254. debug("Saved MRC data with checksum %04x\n", cache->checksum);
  255. else if (ret == -EEXIST)
  256. debug("MRC data is the same as last time, skipping save\n");
  257. return 0;
  258. }
  259. int mrccache_save(void)
  260. {
  261. int i;
  262. for (i = 0; i < MRC_TYPE_COUNT; i++) {
  263. int ret;
  264. ret = mrccache_save_type(i);
  265. if (ret)
  266. return ret;
  267. }
  268. return 0;
  269. }
  270. int mrccache_spl_save(void)
  271. {
  272. int i;
  273. for (i = 0; i < MRC_TYPE_COUNT; i++) {
  274. struct mrc_output *mrc = &gd->arch.mrc[i];
  275. void *data;
  276. int size;
  277. size = mrc->len + MRC_DATA_HEADER_SIZE;
  278. data = malloc(size);
  279. if (!data)
  280. return log_msg_ret("Allocate MRC cache block", -ENOMEM);
  281. mrccache_setup(mrc, data);
  282. }
  283. return mrccache_save();
  284. }