fsp_s.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <acpi_s3.h>
  8. #include <binman.h>
  9. #include <dm.h>
  10. #include <irq.h>
  11. #include <malloc.h>
  12. #include <asm/intel_pinctrl.h>
  13. #include <asm/io.h>
  14. #include <asm/intel_regs.h>
  15. #include <asm/msr.h>
  16. #include <asm/msr-index.h>
  17. #include <asm/pci.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/systemagent.h>
  20. #include <asm/arch/fsp/fsp_configs.h>
  21. #include <asm/arch/fsp/fsp_s_upd.h>
  22. #define PCH_P2SB_E0 0xe0
  23. #define HIDE_BIT BIT(0)
  24. #define INTEL_GSPI_MAX 3
  25. #define MAX_USB2_PORTS 8
  26. enum {
  27. CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
  28. CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
  29. };
  30. /* Serial IRQ control. SERIRQ_QUIET is the default (0) */
  31. enum serirq_mode {
  32. SERIRQ_QUIET,
  33. SERIRQ_CONTINUOUS,
  34. SERIRQ_OFF,
  35. };
  36. struct gspi_cfg {
  37. /* Bus speed in MHz */
  38. u32 speed_mhz;
  39. /* Bus should be enabled prior to ramstage with temporary base */
  40. u8 early_init;
  41. };
  42. /*
  43. * This structure will hold data required by common blocks.
  44. * These are soc specific configurations which will be filled by soc.
  45. * We'll fill this structure once during init and use the data in common block.
  46. */
  47. struct soc_intel_common_config {
  48. int chipset_lockdown;
  49. struct gspi_cfg gspi[INTEL_GSPI_MAX];
  50. };
  51. enum pnp_settings {
  52. PNP_PERF,
  53. PNP_POWER,
  54. PNP_PERF_POWER,
  55. };
  56. struct usb2_eye_per_port {
  57. u8 per_port_tx_pe_half;
  58. u8 per_port_pe_txi_set;
  59. u8 per_port_txi_set;
  60. u8 hs_skew_sel;
  61. u8 usb_tx_emphasis_en;
  62. u8 per_port_rxi_set;
  63. u8 hs_npre_drv_sel;
  64. u8 override_en;
  65. };
  66. struct apl_config {
  67. /* Common structure containing soc config data required by common code*/
  68. struct soc_intel_common_config common_soc_config;
  69. /*
  70. * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
  71. * four CLKREQ inputs, but six root ports. Root ports without an
  72. * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
  73. */
  74. u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
  75. /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
  76. u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
  77. /* De-emphasis enable configuration for each PCIe root port */
  78. u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
  79. /*
  80. * [14:8] DDR mode Number of dealy elements.Each = 125pSec.
  81. * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
  82. */
  83. u32 emmc_tx_cmd_cntl;
  84. /*
  85. * [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
  86. * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
  87. */
  88. u32 emmc_tx_data_cntl1;
  89. /*
  90. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  91. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  92. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  93. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  94. * Each = 125pSec.
  95. */
  96. u32 emmc_tx_data_cntl2;
  97. /*
  98. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  99. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  100. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  101. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  102. * Each = 125pSec.
  103. */
  104. u32 emmc_rx_cmd_data_cntl1;
  105. /*
  106. * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
  107. * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
  108. */
  109. u32 emmc_rx_strobe_cntl;
  110. /*
  111. * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
  112. * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
  113. */
  114. u32 emmc_rx_cmd_data_cntl2;
  115. /* Select the eMMC max speed allowed */
  116. u32 emmc_host_max_speed;
  117. /* Specifies on which IRQ the SCI will internally appear */
  118. u32 sci_irq;
  119. /* Configure serial IRQ (SERIRQ) line */
  120. enum serirq_mode serirq_mode;
  121. /* Configure LPSS S0ix Enable */
  122. bool lpss_s0ix_enable;
  123. /* Enable DPTF support */
  124. bool dptf_enable;
  125. /* TCC activation offset value in degrees Celsius */
  126. int tcc_offset;
  127. /*
  128. * Configure Audio clk gate and power gate
  129. * IOSF-SB port ID 92 offset 0x530 [5] and [3]
  130. */
  131. bool hdaudio_clk_gate_enable;
  132. bool hdaudio_pwr_gate_enable;
  133. bool hdaudio_bios_config_lockdown;
  134. /* SLP S3 minimum assertion width */
  135. int slp_s3_assertion_width_usecs;
  136. /* GPIO pin for PERST_0 */
  137. u32 prt0_gpio;
  138. /* USB2 eye diagram settings per port */
  139. struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
  140. /* GPIO SD card detect pin */
  141. unsigned int sdcard_cd_gpio;
  142. /*
  143. * PRMRR size setting with three options
  144. * 0x02000000 - 32MiB
  145. * 0x04000000 - 64MiB
  146. * 0x08000000 - 128MiB
  147. */
  148. u32 PrmrrSize;
  149. /*
  150. * Enable SGX feature.
  151. * Enabling SGX feature is 2 step process,
  152. * (1) set sgx_enable = 1
  153. * (2) set PrmrrSize to supported size
  154. */
  155. bool sgx_enable;
  156. /*
  157. * Select PNP Settings.
  158. * (0) Performance,
  159. * (1) Power
  160. * (2) Power & Performance
  161. */
  162. enum pnp_settings pnp_settings;
  163. /*
  164. * PMIC PCH_PWROK delay configuration - IPC Configuration
  165. * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
  166. * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
  167. */
  168. u32 pmic_pmc_ipc_ctrl;
  169. /*
  170. * Options to disable XHCI Link Compliance Mode. Default is FALSE to not
  171. * disable Compliance Mode. Set TRUE to disable Compliance Mode.
  172. * 0:FALSE(Default), 1:True.
  173. */
  174. bool disable_compliance_mode;
  175. /*
  176. * Options to change USB3 ModPhy setting for the Integrated Filter (IF)
  177. * value. Default is 0 to not changing default IF value (0x12). Set
  178. * value with the range from 0x01 to 0xff to change IF value.
  179. */
  180. u32 mod_phy_if_value;
  181. /*
  182. * Options to bump USB3 LDO voltage. Default is FALSE to not increasing
  183. * LDO voltage. Set TRUE to increase LDO voltage with 40mV.
  184. * 0:FALSE (default), 1:True.
  185. */
  186. bool mod_phy_voltage_bump;
  187. /*
  188. * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
  189. * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
  190. * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
  191. * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
  192. * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
  193. */
  194. u32 pmic_vdd2_voltage;
  195. /* Option to enable VTD feature */
  196. bool enable_vtd;
  197. };
  198. static int get_config(struct udevice *dev, struct apl_config *apl)
  199. {
  200. const u8 *ptr;
  201. ofnode node;
  202. u32 emmc[4];
  203. int ret;
  204. memset(apl, '\0', sizeof(*apl));
  205. node = dev_read_subnode(dev, "fsp-s");
  206. if (!ofnode_valid(node))
  207. return log_msg_ret("fsp-s settings", -ENOENT);
  208. ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
  209. MAX_PCIE_PORTS);
  210. if (!ptr)
  211. return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
  212. memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
  213. ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
  214. if (ret)
  215. return log_msg_ret("prt0-gpio", ret);
  216. ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
  217. if (ret)
  218. return log_msg_ret("sdcard-cd-gpio", ret);
  219. ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
  220. if (ret)
  221. return log_msg_ret("emmc", ret);
  222. apl->emmc_tx_data_cntl1 = emmc[0];
  223. apl->emmc_tx_data_cntl2 = emmc[1];
  224. apl->emmc_rx_cmd_data_cntl1 = emmc[2];
  225. apl->emmc_rx_cmd_data_cntl2 = emmc[3];
  226. apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
  227. apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
  228. "hdaudio-clk-gate-enable");
  229. apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
  230. "hdaudio-pwr-gate-enable");
  231. apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
  232. "hdaudio-bios-config-lockdown");
  233. apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
  234. /* Santa */
  235. apl->usb2eye[1].per_port_pe_txi_set = 7;
  236. apl->usb2eye[1].per_port_txi_set = 2;
  237. return 0;
  238. }
  239. static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
  240. struct fsp_s_config *cfg)
  241. {
  242. u8 port;
  243. for (port = 0; port < MAX_USB2_PORTS; port++) {
  244. if (apl->usb2eye[port].per_port_tx_pe_half)
  245. cfg->port_usb20_per_port_tx_pe_half[port] =
  246. apl->usb2eye[port].per_port_tx_pe_half;
  247. if (apl->usb2eye[port].per_port_pe_txi_set)
  248. cfg->port_usb20_per_port_pe_txi_set[port] =
  249. apl->usb2eye[port].per_port_pe_txi_set;
  250. if (apl->usb2eye[port].per_port_txi_set)
  251. cfg->port_usb20_per_port_txi_set[port] =
  252. apl->usb2eye[port].per_port_txi_set;
  253. if (apl->usb2eye[port].hs_skew_sel)
  254. cfg->port_usb20_hs_skew_sel[port] =
  255. apl->usb2eye[port].hs_skew_sel;
  256. if (apl->usb2eye[port].usb_tx_emphasis_en)
  257. cfg->port_usb20_i_usb_tx_emphasis_en[port] =
  258. apl->usb2eye[port].usb_tx_emphasis_en;
  259. if (apl->usb2eye[port].per_port_rxi_set)
  260. cfg->port_usb20_per_port_rxi_set[port] =
  261. apl->usb2eye[port].per_port_rxi_set;
  262. if (apl->usb2eye[port].hs_npre_drv_sel)
  263. cfg->port_usb20_hs_npre_drv_sel[port] =
  264. apl->usb2eye[port].hs_npre_drv_sel;
  265. }
  266. }
  267. int fsps_update_config(struct udevice *dev, ulong rom_offset,
  268. struct fsps_upd *upd)
  269. {
  270. struct fsp_s_config *cfg = &upd->config;
  271. struct apl_config *apl;
  272. struct binman_entry vbt;
  273. void *buf;
  274. int ret;
  275. ret = binman_entry_find("intel-vbt", &vbt);
  276. if (ret)
  277. return log_msg_ret("Cannot find VBT", ret);
  278. vbt.image_pos += rom_offset;
  279. buf = malloc(vbt.size);
  280. if (!buf)
  281. return log_msg_ret("Alloc VBT", -ENOMEM);
  282. /*
  283. * Load VBT before devicetree-specific config. This only supports
  284. * memory-mapped SPI at present.
  285. */
  286. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  287. memcpy(buf, (void *)vbt.image_pos, vbt.size);
  288. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  289. if (*(u32 *)buf != VBT_SIGNATURE)
  290. return log_msg_ret("VBT signature", -EINVAL);
  291. cfg->graphics_config_ptr = (ulong)buf;
  292. apl = malloc(sizeof(*apl));
  293. if (!apl)
  294. return log_msg_ret("config", -ENOMEM);
  295. get_config(dev, apl);
  296. cfg->ish_enable = 0;
  297. cfg->enable_sata = 0;
  298. cfg->pcie_root_port_en[2] = 0;
  299. cfg->pcie_rp_hot_plug[2] = 0;
  300. cfg->pcie_root_port_en[3] = 0;
  301. cfg->pcie_rp_hot_plug[3] = 0;
  302. cfg->pcie_root_port_en[4] = 0;
  303. cfg->pcie_rp_hot_plug[4] = 0;
  304. cfg->pcie_root_port_en[5] = 0;
  305. cfg->pcie_rp_hot_plug[5] = 0;
  306. cfg->pcie_root_port_en[1] = 0;
  307. cfg->pcie_rp_hot_plug[1] = 0;
  308. cfg->usb_otg = 0;
  309. cfg->i2c6_enable = 0;
  310. cfg->i2c7_enable = 0;
  311. cfg->hsuart3_enable = 0;
  312. cfg->spi1_enable = 0;
  313. cfg->spi2_enable = 0;
  314. cfg->sdio_enabled = 0;
  315. memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
  316. sizeof(cfg->pcie_rp_clk_req_number));
  317. memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
  318. sizeof(cfg->pcie_rp_hot_plug));
  319. switch (apl->serirq_mode) {
  320. case SERIRQ_QUIET:
  321. cfg->sirq_enable = 1;
  322. cfg->sirq_mode = 0;
  323. break;
  324. case SERIRQ_CONTINUOUS:
  325. cfg->sirq_enable = 1;
  326. cfg->sirq_mode = 1;
  327. break;
  328. case SERIRQ_OFF:
  329. default:
  330. cfg->sirq_enable = 0;
  331. break;
  332. }
  333. if (apl->emmc_tx_cmd_cntl)
  334. cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
  335. if (apl->emmc_tx_data_cntl1)
  336. cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
  337. if (apl->emmc_tx_data_cntl2)
  338. cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
  339. if (apl->emmc_rx_cmd_data_cntl1)
  340. cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
  341. if (apl->emmc_rx_strobe_cntl)
  342. cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
  343. if (apl->emmc_rx_cmd_data_cntl2)
  344. cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
  345. if (apl->emmc_host_max_speed)
  346. cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
  347. cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
  348. cfg->skip_mp_init = true;
  349. /* Disable setting of EISS bit in FSP */
  350. cfg->spi_eiss = 0;
  351. /* Disable FSP from locking access to the RTC NVRAM */
  352. cfg->rtc_lock = 0;
  353. /* Enable Audio clk gate and power gate */
  354. cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
  355. cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
  356. /* Bios config lockdown Audio clk and power gate */
  357. cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
  358. apl_fsp_silicon_init_params_cb(apl, cfg);
  359. cfg->usb_otg = true;
  360. cfg->vtd_enable = apl->enable_vtd;
  361. return 0;
  362. }
  363. static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
  364. {
  365. pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
  366. hide ? HIDE_BIT : 0, PCI_SIZE_8);
  367. }
  368. /* Configure package power limits */
  369. static int set_power_limits(struct udevice *dev)
  370. {
  371. msr_t rapl_msr_reg, limit;
  372. u32 power_unit;
  373. u32 tdp, min_power, max_power;
  374. u32 pl2_val;
  375. u32 override_tdp[2];
  376. int ret;
  377. /* Get units */
  378. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
  379. power_unit = 1 << (rapl_msr_reg.lo & 0xf);
  380. /* Get power defaults for this SKU */
  381. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
  382. tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
  383. pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  384. min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
  385. max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  386. if (min_power > 0 && tdp < min_power)
  387. tdp = min_power;
  388. if (max_power > 0 && tdp > max_power)
  389. tdp = max_power;
  390. ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
  391. ARRAY_SIZE(override_tdp));
  392. if (ret)
  393. return log_msg_ret("tdp-pl-override-mw", ret);
  394. /* Set PL1 override value */
  395. if (override_tdp[0])
  396. tdp = override_tdp[0] * power_unit / 1000;
  397. /* Set PL2 override value */
  398. if (override_tdp[1])
  399. pl2_val = override_tdp[1] * power_unit / 1000;
  400. /* Set long term power limit to TDP */
  401. limit.lo = tdp & PKG_POWER_LIMIT_MASK;
  402. /* Set PL1 Pkg Power clamp bit */
  403. limit.lo |= PKG_POWER_LIMIT_CLAMP;
  404. limit.lo |= PKG_POWER_LIMIT_EN;
  405. limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
  406. PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
  407. /* Set short term power limit PL2 */
  408. limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
  409. limit.hi |= PKG_POWER_LIMIT_EN;
  410. /* Program package power limits in RAPL MSR */
  411. msr_write(MSR_PKG_POWER_LIMIT, limit);
  412. log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
  413. 100 * (tdp % power_unit) / power_unit);
  414. log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
  415. 100 * (pl2_val % power_unit) / power_unit);
  416. /*
  417. * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
  418. * instead of MMIO, so disable LIMIT_EN bit for MMIO
  419. */
  420. writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
  421. writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
  422. return 0;
  423. }
  424. int p2sb_unhide(void)
  425. {
  426. pci_dev_t dev = PCI_BDF(0, 0xd, 0);
  427. ulong val;
  428. p2sb_set_hide_bit(dev, 0);
  429. pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
  430. if (val != PCI_VENDOR_ID_INTEL)
  431. return log_msg_ret("p2sb unhide", -EIO);
  432. return 0;
  433. }
  434. /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
  435. static void set_sci_irq(void)
  436. {
  437. /* Skip this for now */
  438. }
  439. int arch_fsps_preinit(void)
  440. {
  441. struct udevice *itss;
  442. int ret;
  443. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  444. if (ret)
  445. return log_msg_ret("no itss", ret);
  446. /*
  447. * Snapshot the current GPIO IRQ polarities. FSP is setting a default
  448. * policy that doesn't honour boards' requirements
  449. */
  450. irq_snapshot_polarities(itss);
  451. /*
  452. * Clear the GPI interrupt status and enable registers. These
  453. * registers do not get reset to default state when booting from S5.
  454. */
  455. ret = pinctrl_gpi_clear_int_cfg();
  456. if (ret)
  457. return log_msg_ret("gpi_clear", ret);
  458. return 0;
  459. }
  460. int arch_fsp_init_r(void)
  461. {
  462. #ifdef CONFIG_HAVE_ACPI_RESUME
  463. bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
  464. #else
  465. bool s3wake = false;
  466. #endif
  467. struct udevice *dev, *itss;
  468. int ret;
  469. /*
  470. * This must be called before any devices are probed. Put any probing
  471. * into arch_fsps_preinit() above.
  472. *
  473. * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
  474. * force PCI to be probed.
  475. */
  476. ret = fsp_silicon_init(s3wake, false);
  477. if (ret)
  478. return ret;
  479. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  480. if (ret)
  481. return log_msg_ret("no itss", ret);
  482. /* Restore GPIO IRQ polarities back to previous settings */
  483. irq_restore_polarities(itss);
  484. /* soc_init() */
  485. ret = p2sb_unhide();
  486. if (ret)
  487. return log_msg_ret("unhide p2sb", ret);
  488. /* Set RAPL MSR for Package power limits*/
  489. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
  490. if (ret)
  491. return log_msg_ret("Cannot get northbridge", ret);
  492. set_power_limits(dev);
  493. /*
  494. * FSP-S routes SCI to IRQ 9. With the help of this function you can
  495. * select another IRQ for SCI.
  496. */
  497. set_sci_irq();
  498. return 0;
  499. }