clk.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
  4. * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <malloc.h>
  10. #include <asm/arch/clk.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. static const char * const clk_names[clk_max] = {
  13. "armpll", "ddrpll", "iopll",
  14. "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  15. "ddr2x", "ddr3x", "dci",
  16. "lqspi", "smc", "pcap", "gem0", "gem1",
  17. "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  18. "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  19. "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  20. "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  21. "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  22. "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  23. "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  24. };
  25. /**
  26. * set_cpu_clk_info() - Setup clock information
  27. *
  28. * This function is called from common code after relocation and sets up the
  29. * clock information.
  30. */
  31. int set_cpu_clk_info(void)
  32. {
  33. struct clk clk;
  34. struct udevice *dev;
  35. ulong rate;
  36. int i, ret;
  37. ret = uclass_get_device_by_driver(UCLASS_CLK,
  38. DM_GET_DRIVER(zynq_clk), &dev);
  39. if (ret)
  40. return ret;
  41. for (i = 0; i < 2; i++) {
  42. clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  43. ret = clk_request(dev, &clk);
  44. if (ret < 0)
  45. return ret;
  46. rate = clk_get_rate(&clk) / 1000000;
  47. if (i)
  48. gd->bd->bi_ddr_freq = rate;
  49. else
  50. gd->bd->bi_arm_freq = rate;
  51. clk_free(&clk);
  52. }
  53. gd->bd->bi_dsp_freq = 0;
  54. return 0;
  55. }
  56. /**
  57. * soc_clk_dump() - Print clock frequencies
  58. * Returns zero on success
  59. *
  60. * Implementation for the clk dump command.
  61. */
  62. int soc_clk_dump(void)
  63. {
  64. struct udevice *dev;
  65. int i, ret;
  66. ret = uclass_get_device_by_driver(UCLASS_CLK,
  67. DM_GET_DRIVER(zynq_clk), &dev);
  68. if (ret)
  69. return ret;
  70. printf("clk\t\tfrequency\n");
  71. for (i = 0; i < clk_max; i++) {
  72. const char *name = clk_names[i];
  73. if (name) {
  74. struct clk clk;
  75. unsigned long rate;
  76. clk.id = i;
  77. ret = clk_request(dev, &clk);
  78. if (ret < 0)
  79. return ret;
  80. rate = clk_get_rate(&clk);
  81. clk_free(&clk);
  82. if ((rate == (unsigned long)-ENOSYS) ||
  83. (rate == (unsigned long)-ENXIO))
  84. printf("%10s%20s\n", name, "unknown");
  85. else
  86. printf("%10s%20lu\n", name, rate);
  87. }
  88. }
  89. return 0;
  90. }