rk3308.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *Copyright (c) 2018 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/grf_rk3308.h>
  9. #include <asm/arch-rockchip/hardware.h>
  10. #include <asm/gpio.h>
  11. #include <debug_uart.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #include <asm/armv8/mmu.h>
  14. static struct mm_region rk3308_mem_map[] = {
  15. {
  16. .virt = 0x0UL,
  17. .phys = 0x0UL,
  18. .size = 0xff000000UL,
  19. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  20. PTE_BLOCK_INNER_SHARE
  21. }, {
  22. .virt = 0xff000000UL,
  23. .phys = 0xff000000UL,
  24. .size = 0x01000000UL,
  25. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26. PTE_BLOCK_NON_SHARE |
  27. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  28. }, {
  29. /* List terminator */
  30. 0,
  31. }
  32. };
  33. struct mm_region *mem_map = rk3308_mem_map;
  34. #define GRF_BASE 0xff000000
  35. #define SGRF_BASE 0xff2b0000
  36. enum {
  37. GPIO1C7_SHIFT = 8,
  38. GPIO1C7_MASK = GENMASK(11, 8),
  39. GPIO1C7_GPIO = 0,
  40. GPIO1C7_UART1_RTSN,
  41. GPIO1C7_UART2_TX_M0,
  42. GPIO1C7_SPI2_MOSI,
  43. GPIO1C7_JTAG_TMS,
  44. GPIO1C6_SHIFT = 4,
  45. GPIO1C6_MASK = GENMASK(7, 4),
  46. GPIO1C6_GPIO = 0,
  47. GPIO1C6_UART1_CTSN,
  48. GPIO1C6_UART2_RX_M0,
  49. GPIO1C6_SPI2_MISO,
  50. GPIO1C6_JTAG_TCLK,
  51. GPIO4D3_SHIFT = 6,
  52. GPIO4D3_MASK = GENMASK(7, 6),
  53. GPIO4D3_GPIO = 0,
  54. GPIO4D3_SDMMC_D3,
  55. GPIO4D3_UART2_TX_M1,
  56. GPIO4D2_SHIFT = 4,
  57. GPIO4D2_MASK = GENMASK(5, 4),
  58. GPIO4D2_GPIO = 0,
  59. GPIO4D2_SDMMC_D2,
  60. GPIO4D2_UART2_RX_M1,
  61. UART2_IO_SEL_SHIFT = 2,
  62. UART2_IO_SEL_MASK = GENMASK(3, 2),
  63. UART2_IO_SEL_M0 = 0,
  64. UART2_IO_SEL_M1,
  65. UART2_IO_SEL_USB,
  66. GPIO2C0_SEL_SRC_CTRL_SHIFT = 11,
  67. GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11),
  68. GPIO2C0_SEL_SRC_CTRL_IOMUX = 0,
  69. GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
  70. GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
  71. GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
  72. GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
  73. GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
  74. GPIO3B3_SEL_PLUS_SHIFT = 4,
  75. GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4),
  76. GPIO3B3_SEL_PLUS_GPIO3_B3 = 0,
  77. GPIO3B3_SEL_PLUS_FLASH_ALE,
  78. GPIO3B3_SEL_PLUS_EMMC_PWREN,
  79. GPIO3B3_SEL_PLUS_SPI1_CLK,
  80. GPIO3B3_SEL_PLUS_LCDC_D23_M1,
  81. GPIO3B2_SEL_SRC_CTRL_SHIFT = 3,
  82. GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3),
  83. GPIO3B2_SEL_SRC_CTRL_IOMUX = 0,
  84. GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
  85. GPIO3B2_SEL_PLUS_SHIFT = 0,
  86. GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0),
  87. GPIO3B2_SEL_PLUS_GPIO3_B2 = 0,
  88. GPIO3B2_SEL_PLUS_FLASH_RDN,
  89. GPIO3B2_SEL_PLUS_EMMC_RSTN,
  90. GPIO3B2_SEL_PLUS_SPI1_MISO,
  91. GPIO3B2_SEL_PLUS_LCDC_D22_M1,
  92. I2C3_IOFUNC_SRC_CTRL_SHIFT = 10,
  93. I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10),
  94. I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1,
  95. GPIO2A3_SEL_SRC_CTRL_SHIFT = 7,
  96. GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7),
  97. GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1,
  98. GPIO2A2_SEL_SRC_CTRL_SHIFT = 3,
  99. GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3),
  100. GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1,
  101. };
  102. enum {
  103. IOVSEL3_CTRL_SHIFT = 8,
  104. IOVSEL3_CTRL_MASK = BIT(8),
  105. VCCIO3_SEL_BY_GPIO = 0,
  106. VCCIO3_SEL_BY_IOVSEL3,
  107. IOVSEL3_SHIFT = 3,
  108. IOVSEL3_MASK = BIT(3),
  109. VCCIO3_3V3 = 0,
  110. VCCIO3_1V8,
  111. };
  112. /*
  113. * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
  114. * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
  115. * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
  116. * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
  117. * for other usage.
  118. */
  119. #define GPIO0_A4 4
  120. int rk_board_init(void)
  121. {
  122. static struct rk3308_grf * const grf = (void *)GRF_BASE;
  123. u32 val;
  124. int ret;
  125. ret = gpio_request(GPIO0_A4, "gpio0_a4");
  126. if (ret < 0) {
  127. printf("request for gpio0_a4 failed:%d\n", ret);
  128. return 0;
  129. }
  130. gpio_direction_input(GPIO0_A4);
  131. if (gpio_get_value(GPIO0_A4))
  132. val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
  133. VCCIO3_1V8 << IOVSEL3_SHIFT;
  134. else
  135. val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
  136. VCCIO3_3V3 << IOVSEL3_SHIFT;
  137. rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
  138. gpio_free(GPIO0_A4);
  139. return 0;
  140. }
  141. #if defined(CONFIG_DEBUG_UART)
  142. __weak void board_debug_uart_init(void)
  143. {
  144. static struct rk3308_grf * const grf = (void *)GRF_BASE;
  145. /* Enable early UART2 channel m1 on the rk3308 */
  146. rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
  147. UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
  148. rk_clrsetreg(&grf->gpio4d_iomux,
  149. GPIO4D3_MASK | GPIO4D2_MASK,
  150. GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
  151. GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
  152. }
  153. #endif
  154. #if defined(CONFIG_SPL_BUILD)
  155. int arch_cpu_init(void)
  156. {
  157. static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
  158. static struct rk3308_grf * const grf = (void *)GRF_BASE;
  159. /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
  160. rk_clrreg(&sgrf->con_secure0, 0x2b83);
  161. /*
  162. * Enable plus options to use more pinctrl functions, including
  163. * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
  164. */
  165. rk_clrsetreg(&grf->soc_con13,
  166. I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
  167. GPIO2A2_SEL_SRC_CTRL_MASK,
  168. I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
  169. GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
  170. GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
  171. /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
  172. rk_clrsetreg(&grf->soc_con15,
  173. GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
  174. GPIO3B2_SEL_SRC_CTRL_MASK,
  175. GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
  176. GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
  177. GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
  178. return 0;
  179. }
  180. #endif