rk3288.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <env.h>
  8. #include <clk.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <asm/armv7.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/bootrom.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/cru.h>
  16. #include <asm/arch-rockchip/hardware.h>
  17. #include <asm/arch-rockchip/grf_rk3288.h>
  18. #include <asm/arch-rockchip/pmu_rk3288.h>
  19. #include <asm/arch-rockchip/qos_rk3288.h>
  20. #include <asm/arch-rockchip/sdram.h>
  21. #include <linux/err.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define GRF_BASE 0xff770000
  24. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  25. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  26. [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  27. };
  28. #ifdef CONFIG_SPL_BUILD
  29. static void configure_l2ctlr(void)
  30. {
  31. u32 l2ctlr;
  32. l2ctlr = read_l2ctlr();
  33. l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  34. /*
  35. * Data RAM write latency: 2 cycles
  36. * Data RAM read latency: 2 cycles
  37. * Data RAM setup latency: 1 cycle
  38. * Tag RAM write latency: 1 cycle
  39. * Tag RAM read latency: 1 cycle
  40. * Tag RAM setup latency: 1 cycle
  41. */
  42. l2ctlr |= (1 << 3 | 1 << 0);
  43. write_l2ctlr(l2ctlr);
  44. }
  45. #endif
  46. int rk3288_qos_init(void)
  47. {
  48. int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  49. /* set vop qos to higher priority */
  50. writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  51. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  52. if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  53. "rockchip,rk3288-tinker")) {
  54. /* set isp qos to higher priority */
  55. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  56. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  57. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  58. }
  59. return 0;
  60. }
  61. int arch_cpu_init(void)
  62. {
  63. #ifdef CONFIG_SPL_BUILD
  64. configure_l2ctlr();
  65. #else
  66. /* We do some SoC one time setting here. */
  67. struct rk3288_grf * const grf = (void *)GRF_BASE;
  68. /* Use rkpwm by default */
  69. rk_setreg(&grf->soc_con2, 1 << 0);
  70. /*
  71. * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  72. * cleared
  73. */
  74. rk_clrreg(&grf->soc_con0, 1 << 12);
  75. rk3288_qos_init();
  76. #endif
  77. return 0;
  78. }
  79. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  80. void board_debug_uart_init(void)
  81. {
  82. /* Enable early UART on the RK3288 */
  83. struct rk3288_grf * const grf = (void *)GRF_BASE;
  84. rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
  85. GPIO7C6_MASK << GPIO7C6_SHIFT,
  86. GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
  87. GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
  88. }
  89. #endif
  90. __weak int rk3288_board_late_init(void)
  91. {
  92. return 0;
  93. }
  94. int rk_board_late_init(void)
  95. {
  96. return rk3288_board_late_init();
  97. }
  98. static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
  99. char * const argv[])
  100. {
  101. static const struct {
  102. char *name;
  103. int id;
  104. } clks[] = {
  105. { "osc", CLK_OSC },
  106. { "apll", CLK_ARM },
  107. { "dpll", CLK_DDR },
  108. { "cpll", CLK_CODEC },
  109. { "gpll", CLK_GENERAL },
  110. #ifdef CONFIG_ROCKCHIP_RK3036
  111. { "mpll", CLK_NEW },
  112. #else
  113. { "npll", CLK_NEW },
  114. #endif
  115. };
  116. int ret, i;
  117. struct udevice *dev;
  118. ret = rockchip_get_clk(&dev);
  119. if (ret) {
  120. printf("clk-uclass not found\n");
  121. return 0;
  122. }
  123. for (i = 0; i < ARRAY_SIZE(clks); i++) {
  124. struct clk clk;
  125. ulong rate;
  126. clk.id = clks[i].id;
  127. ret = clk_request(dev, &clk);
  128. if (ret < 0)
  129. continue;
  130. rate = clk_get_rate(&clk);
  131. printf("%s: %lu\n", clks[i].name, rate);
  132. clk_free(&clk);
  133. }
  134. return 0;
  135. }
  136. U_BOOT_CMD(
  137. clock, 2, 1, do_clock,
  138. "display information about clocks",
  139. ""
  140. );